GB1491705A - Semiconductor junctions - Google Patents

Semiconductor junctions

Info

Publication number
GB1491705A
GB1491705A GB2648074A GB2648074A GB1491705A GB 1491705 A GB1491705 A GB 1491705A GB 2648074 A GB2648074 A GB 2648074A GB 2648074 A GB2648074 A GB 2648074A GB 1491705 A GB1491705 A GB 1491705A
Authority
GB
United Kingdom
Prior art keywords
grooves
semi
filling
conductivity type
cut
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB2648074A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Ltd
Original Assignee
Texas Instruments Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Ltd filed Critical Texas Instruments Ltd
Priority to GB2648074A priority Critical patent/GB1491705A/en
Publication of GB1491705A publication Critical patent/GB1491705A/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304Mechanical treatment, e.g. grinding, polishing, cutting
    • H01L21/3046Mechanical treatment, e.g. grinding, polishing, cutting using blasting, e.g. sand-blasting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304Mechanical treatment, e.g. grinding, polishing, cutting
    • H01L21/3043Making grooves, e.g. cutting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157Partial encapsulation or coating
    • H01L23/3178Coating or filling in grooves made in the semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0661Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Dicing (AREA)
  • Bipolar Transistors (AREA)

Abstract

1491705 Semi-conductor devices TEXAS INSTRUMENTS Ltd 20 Dec 1974 [14 June 1974] 26480/75 Heading H1K A semi-conductor device is made from a wafer comprising a low resistivity substrate member of one conductivity type with a high resistivity layer of the same type and an overlying layer of the opposite conductivity type disposed thereon by mechanically cutting a closed channel extending through the layers to the member and providing an included angle >90 degrees at the upper edge of the high resistivity layer, removing damaged material from the channel by chemical etching, filling it with a glass and encapsulating the device in mouldable material. In the described methods transistor structures (Fig. 2) are defined in a layered silicon wafer, formed by conventional diffusion and epitaxy techniques, by intersecting sets of grooves cut through the base and collector regions 3, 1 to collector contact region 2. After filling the grooves with lead aluminosilicate glass the structures are separated along lines 11 by sawing or deep laser scribing and encapsulated in epoxy resin. The grooves, cut by a diamondloaded saw blade, ultrasonically agitated tool, or preferably by a jet of air or water loaded with abrasive particles may be as shown or in the form of vertical or inwardly inclined parallel sided slots.
GB2648074A 1974-12-20 1974-12-20 Semiconductor junctions Expired GB1491705A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB2648074A GB1491705A (en) 1974-12-20 1974-12-20 Semiconductor junctions

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB2648074A GB1491705A (en) 1974-12-20 1974-12-20 Semiconductor junctions

Publications (1)

Publication Number Publication Date
GB1491705A true GB1491705A (en) 1977-11-16

Family

ID=10244310

Family Applications (1)

Application Number Title Priority Date Filing Date
GB2648074A Expired GB1491705A (en) 1974-12-20 1974-12-20 Semiconductor junctions

Country Status (1)

Country Link
GB (1) GB1491705A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2468207A1 (en) * 1979-10-23 1981-04-30 Thomson Csf Separation slot structure in semiconductors - has shallow V=shape esp. for mesa structures obtained by chemical attack or mechanical grinding
DE3218953A1 (en) * 1981-05-20 1983-01-05 Tokyo Shibaura Electric Co METHOD AND DEVICE FOR FORMING AN ANGLE IN A SEMICONDUCTOR DEVICE
EP0075103A2 (en) * 1981-09-22 1983-03-30 Siemens Aktiengesellschaft Thyristor with a multi-layer semiconductor body and process for its manufacture
EP0228863A2 (en) * 1985-12-20 1987-07-15 Seiko Instruments Inc. Method of dividing a substrate into a plurality of substrate portions
US5313092A (en) * 1989-05-12 1994-05-17 Nippon Soken, Inc. Semiconductor power device having walls of an inverted mesa shape to improve power handling capability

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2468207A1 (en) * 1979-10-23 1981-04-30 Thomson Csf Separation slot structure in semiconductors - has shallow V=shape esp. for mesa structures obtained by chemical attack or mechanical grinding
DE3218953A1 (en) * 1981-05-20 1983-01-05 Tokyo Shibaura Electric Co METHOD AND DEVICE FOR FORMING AN ANGLE IN A SEMICONDUCTOR DEVICE
US4517769A (en) * 1981-05-20 1985-05-21 Tokyo Shibaura Denki Kabushiki Kaisha Method and apparatus for forming oblique groove in semiconductor device
EP0075103A2 (en) * 1981-09-22 1983-03-30 Siemens Aktiengesellschaft Thyristor with a multi-layer semiconductor body and process for its manufacture
EP0075103A3 (en) * 1981-09-22 1983-09-28 Siemens Aktiengesellschaft Thyristor with a multi-layer semiconductor body and process for its manufacture
EP0228863A2 (en) * 1985-12-20 1987-07-15 Seiko Instruments Inc. Method of dividing a substrate into a plurality of substrate portions
EP0228863A3 (en) * 1985-12-20 1988-03-09 Seiko Instruments Inc. Method of dividing a substrate into a plurality of substrate portions
US5313092A (en) * 1989-05-12 1994-05-17 Nippon Soken, Inc. Semiconductor power device having walls of an inverted mesa shape to improve power handling capability

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Legal Events

Date Code Title Description
PS Patent sealed
PCNP Patent ceased through non-payment of renewal fee