GB1445414A - Input/output control apparatus - Google Patents
Input/output control apparatusInfo
- Publication number
- GB1445414A GB1445414A GB4235973A GB4235973A GB1445414A GB 1445414 A GB1445414 A GB 1445414A GB 4235973 A GB4235973 A GB 4235973A GB 4235973 A GB4235973 A GB 4235973A GB 1445414 A GB1445414 A GB 1445414A
- Authority
- GB
- United Kingdom
- Prior art keywords
- controller
- bits
- instructions
- input
- unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/12—Digital output to print unit, e.g. line printer, chain printer
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Human Computer Interaction (AREA)
- Bus Control (AREA)
- Control By Computers (AREA)
Abstract
1445414 Input/output controller INTERNATIONAL BUSINESS MACHINES CORP 8 Sept 1973 42359/73 Heading G4A [Also in Division H4] Input/output control apparatus for connection between an input/output device and a central controller includes a sequence unit arranged to follow selected sequences of operations in various modes in response to instructions from the controller. The apparatus includes a parallel-serial converter 6 for receiving three eight bit bytes in parallel from an associated peripheral, and transmitting data serially over bus 3 to the controller. An output buffer 7 is provided to staticize serial data from the controller via bus 2 for transmission to the peripheral. An input buffer 47 is also provided for storing data from the peripheral for subsequent transmission to the controller. A control unit 9 receives instructions from the controller and provides control signals to the remainder of the system. The controller includes a four-bit hard wired address and provision for storing an address supplied by the controller. The control unit 9 also includes provision for handling interrupts from the system as described in Specification 1,365,838. The sequence unit 12 receives instructions from bus 2 and responds to the instructions to control the input buffer 7, output buffer 47 and counting operations. The sequence unit, Fig. 3, responds to instructions in the form of three eight bit bytes stored in registers 13 and 14, two sets of registers 13, 14 being provided to reduce the number of times the unit has to access the controller to receive instructions. The first instruction byte contains two bits C specifying one of four modes of operation which are decoded at 21 to control the gates P-V, (the gates A-G and H-N being actuated in response to instructions decoded by the control unit 9) two bits B specifying those trigger signals to which unit 22 is to respond, unit 22 being able to receive two eight bit masking instructions from the controller, and four bits A which specify a division ratio for the pulses supplied by oscillator 20. The second byte consists of eight bits D specifying the number of pulses to be counted by counter 25 in a timing operation, comparator 27 providing a signal to indicate the end of the time interval, the third byte consists of four bits G specifying a particular operation, two bits F specifying the operation which is to follow, which may be no operation, the same operation repeated, or the operation specified by the other instruction in registers 13, 14, and two bits E storing interrupt conditions for the controller as a result of an executed operation. The four modes of operation involve (I) initiating an input/output operation a given time after the occurrence of a stimulus, the time being given by a fixed number (determined by the second instruction byte) of pulses derived by dividing the frequency of oscillator 20 by a value determined by the bits A of the first instruction byte, and the stimulus being determined by the B bits of the first instruction byte, (II) initiating an I/O operation followed by a given time delay, (III) as (I) above but restarting the count from zero each time the specified stimulus occurs, and (IV) initiating an I/O operation when a specified stimulus has occurred a given number of times specified by the second instruction byte. Decoder 21 controls gates P-V to provide the desired mode of operation, e.g. in mode (IV) a trigger signal on lines 23 is recognized using bits B of byte 1 and the number of times the stimulus occurs is counted by counter 25 (gate R opened) until comparator provides a signal (via gate V) to actuate unit 30 which initiates the operation specified by bits G of the third instruction byte. Completion of an operation, e.g. sending data from an input device to input buffer 47 may signal an interrupt using the E bits of instruction byte 3, in this case the interrupt signal requires the controller to receive the data stored in the input buffer. Depending on the operation involved the operation which is to follow a completed operation may be inhibited pending cancellation of the interrupt signal, e.g. in the above case the controller accepts the data from input buffer 47 to cancel the interrupt. Operations involved in controlling an on-thefly printer are described.
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB4235973A GB1445414A (en) | 1973-09-08 | 1973-09-08 | Input/output control apparatus |
IT2510174A IT1017114B (en) | 1973-09-08 | 1974-07-12 | PERFECTED SYSTEM FOR DATA PROCESSING |
FR7427485A FR2243475B1 (en) | 1973-09-08 | 1974-08-02 | |
JP10060974A JPS5423772B2 (en) | 1973-09-08 | 1974-09-03 | |
DE19742442772 DE2442772C2 (en) | 1973-09-08 | 1974-09-06 | Universal connection module |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB4235973A GB1445414A (en) | 1973-09-08 | 1973-09-08 | Input/output control apparatus |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1445414A true GB1445414A (en) | 1976-08-11 |
Family
ID=10424067
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB4235973A Expired GB1445414A (en) | 1973-09-08 | 1973-09-08 | Input/output control apparatus |
Country Status (5)
Country | Link |
---|---|
JP (1) | JPS5423772B2 (en) |
DE (1) | DE2442772C2 (en) |
FR (1) | FR2243475B1 (en) |
GB (1) | GB1445414A (en) |
IT (1) | IT1017114B (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2342738A (en) * | 1998-07-09 | 2000-04-19 | Bosch Gmbh Robert | Buffered peripheral-controller |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2307407A1 (en) * | 1975-04-09 | 1976-11-05 | Singer Co | Data interface module for connecting subsystems - couples subsystems to common transmission line by coding outgoing and decoding incoming signals |
IT1150998B (en) * | 1980-09-02 | 1986-12-17 | Telecomucicazioni Siemens Spa | CONTROL UNIT OF AN INPUT-OUTPUT MODULE OF AN ELECTRONIC PROCESSOR |
-
1973
- 1973-09-08 GB GB4235973A patent/GB1445414A/en not_active Expired
-
1974
- 1974-07-12 IT IT2510174A patent/IT1017114B/en active
- 1974-08-02 FR FR7427485A patent/FR2243475B1/fr not_active Expired
- 1974-09-03 JP JP10060974A patent/JPS5423772B2/ja not_active Expired
- 1974-09-06 DE DE19742442772 patent/DE2442772C2/en not_active Expired
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2342738A (en) * | 1998-07-09 | 2000-04-19 | Bosch Gmbh Robert | Buffered peripheral-controller |
GB2342738B (en) * | 1998-07-09 | 2001-07-11 | Bosch Gmbh Robert | Digital interface unit |
US6480910B1 (en) | 1998-07-09 | 2002-11-12 | Robert Bosch Gmbh | Digital interface unit with selective input registers providing control values to output registers that simultaneously output the control values when activated by control line |
Also Published As
Publication number | Publication date |
---|---|
JPS5423772B2 (en) | 1979-08-16 |
IT1017114B (en) | 1977-07-20 |
FR2243475A1 (en) | 1975-04-04 |
DE2442772A1 (en) | 1975-03-13 |
DE2442772C2 (en) | 1982-09-09 |
FR2243475B1 (en) | 1976-10-22 |
JPS50124541A (en) | 1975-09-30 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed | ||
PCNP | Patent ceased through non-payment of renewal fee |