GB1445414A - Input/output control apparatus - Google Patents

Abstract

1445414 Input/output controller INTERNATIONAL BUSINESS MACHINES CORP 8 Sept 1973 42359/73 Heading G4A [Also in Division H4] Input/output control apparatus for connection between an input/output device and a central controller includes a sequence unit arranged to follow selected sequences of operations in various modes in response to instructions from the controller. The apparatus includes a parallel-serial converter 6 for receiving three eight bit bytes in parallel from an associated peripheral, and transmitting data serially over bus 3 to the controller. An output buffer 7 is provided to staticize serial data from the controller via bus 2 for transmission to the peripheral. An input buffer 47 is also provided for storing data from the peripheral for subsequent transmission to the controller. A control unit 9 receives instructions from the controller and provides control signals to the remainder of the system. The controller includes a four-bit hard wired address and provision for storing an address supplied by the controller. The control unit 9 also includes provision for handling interrupts from the system as described in Specification 1,365,838. The sequence unit 12 receives instructions from bus 2 and responds to the instructions to control the input buffer 7, output buffer 47 and counting operations. The sequence unit, Fig. 3, responds to instructions in the form of three eight bit bytes stored in registers 13 and 14, two sets of registers 13, 14 being provided to reduce the number of times the unit has to access the controller to receive instructions. The first instruction byte contains two bits C specifying one of four modes of operation which are decoded at 21 to control the gates P-V, (the gates A-G and H-N being actuated in response to instructions decoded by the control unit 9) two bits B specifying those trigger signals to which unit 22 is to respond, unit 22 being able to receive two eight bit masking instructions from the controller, and four bits A which specify a division ratio for the pulses supplied by oscillator 20. The second byte consists of eight bits D specifying the number of pulses to be counted by counter 25 in a timing operation, comparator 27 providing a signal to indicate the end of the time interval, the third byte consists of four bits G specifying a particular operation, two bits F specifying the operation which is to follow, which may be no operation, the same operation repeated, or the operation specified by the other instruction in registers 13, 14, and two bits E storing interrupt conditions for the controller as a result of an executed operation. The four modes of operation involve (I) initiating an input/output operation a given time after the occurrence of a stimulus, the time being given by a fixed number (determined by the second instruction byte) of pulses derived by dividing the frequency of oscillator 20 by a value determined by the bits A of the first instruction byte, and the stimulus being determined by the B bits of the first instruction byte, (II) initiating an I/O operation followed by a given time delay, (III) as (I) above but restarting the count from zero each time the specified stimulus occurs, and (IV) initiating an I/O operation when a specified stimulus has occurred a given number of times specified by the second instruction byte. Decoder 21 controls gates P-V to provide the desired mode of operation, e.g. in mode (IV) a trigger signal on lines 23 is recognized using bits B of byte 1 and the number of times the stimulus occurs is counted by counter 25 (gate R opened) until comparator provides a signal (via gate V) to actuate unit 30 which initiates the operation specified by bits G of the third instruction byte. Completion of an operation, e.g. sending data from an input device to input buffer 47 may signal an interrupt using the E bits of instruction byte 3, in this case the interrupt signal requires the controller to receive the data stored in the input buffer. Depending on the operation involved the operation which is to follow a completed operation may be inhibited pending cancellation of the interrupt signal, e.g. in the above case the controller accepts the data from input buffer 47 to cancel the interrupt. Operations involved in controlling an on-thefly printer are described.