1432934 Data transmission; coding systems; pictorial transmission INTERNATIONAL PUBLISHING CORP Ltd 2 April 1973 [10 April 1972] 55398/71 Heading H4P A coding arrangement comprises predicting from p received symbols, future symbol transitions which are compared with incoming symbols to produce an error which is coded for transmission. The predictor includes circuits having a polynomial characteristic, one of which nearest to at least one received group of signals being selected for prediction process. The predictor output is coded in one of a plurality of different coders the subject of Specification 1,432,935, outputs from which are monitored to select the one with shortest coded output for transmission together with an identifying character which enables a corresponding coder at a receiver. A nil coder may be included to give 1 : 1 input/output. The arrangement may be utilized in a facsimile or TV system for reducing redundancy. Between 1-4 scans may be used for prediction either by lines or blocks. Procedure is to fit the nearest lowest order polynome to extrapolate the next scan. For prediction based on one line, a zero order, two lines a first order and three lines second order polynomes are suitable. Complicated patterns can be segmented into simpler ones. A modification is included for prediction that produces transitions which would be out of sequence which is remedied by comparing all predicted transitions each with its successor and removing those that will be reproduced in reverse order; the successor is also removed so that transitions are always removed in pairs. An error signal is developed from comparison of predicted and actual which is preferably run length in form. Counter 20 measures elements in a scan line. One prediction process uses two previous scan lines held in circulating stores (3) (see Fig. 1 not shown) in which each element in the two lines is compared to generate signals TR1, TR2. As a facsimile drum (1a) rotates, occurrence of a transition on either of two previous scans causes content of counter 20, counting run length bits of each type, to be transferred to bi-stable latch (Figs. 1 or 2) comprising multiple bit stores, for temporary storage. A third latch 3 contains the position of penultimate transition of scan 1, whereas latch 1 has the last occurring transition. The prediction process is based on preestablished identifiable patterns (see for example Fig. 3, not shown) and these are determined by a transition state counter 21 and transition number 22. It is assumed that on every second transition, counter 21 will progress through counts indicated on a prediction tree (see Fig. 6, not shown) which are recognized by a transition state number decoder 23, outputs from which control presentation of correct combinations from latches 1-3 via gates 25 to an arithmetic adder 24 which produces a sequence of binary numbers defining transition positions to buffer store 1. The number of patterns is deliberately limited to at most 6 transitions, more complex patterns being segmented. At the end of each prediction 21, 22 are reset. The generation of a first order polynome x = 2x 1 - x 2 (see Fig. 2, not shown) corresponding to prediction based on two previous scan lines, gates 25 connect complementary outputs of one latch and twice output of second latch to adder 24. Each count from 24 is compared with previous count to ensure that present count is greater before storing in store 1. If not both counts are removed from a sequence. On completion of each line, prediction of next scan line will be placed in buffer 4a. The error is produced by a circuit given in Fig. 8 (not shown) similar to Fig. 7 in which a present incoming scan line (or block) delayed by one line (or block) time is compared with the predicted sequence. The error signal for each pattern comprises a code word identifying the pattern plus sufficient information to enable a receiver to derive a replica of the original from an identical prediction made at the receiver. Error signals for correcting positions of transitions predicted at the receiver are derived from correct selection of run length counts from (36) and stored in latches (A-D) for processing by adder (34) and passing to store (5a). A set of pattern code words is stored in (35) which are transmitted before error signals. Before transmission, each error word is represented to parallel coders (6) (Fig. 9, not shown), output from which fills an associated store (40) each co-operating with an address counter and decoder (41, 42) which store content is dumped into a latch circuit for subsequent selection by arithmetic unit (44). Initially one of the coders has priority until (44) replaces it to provide optimum number of bits transmitted. To avoid use of large output buffer stores acting as a reservoir between generated and transmitted bits, further scans can be arrested temporarily or in the case of a CRT scanner scan velocity may be varied. However a large buffer store, storing complete documents may be of value in a store and forward system, also for networks of facsimile subscribers utilizing common compression equipment.