GB1432309A - Semiconductor structures - Google Patents

Semiconductor structures

Info

Publication number
GB1432309A
GB1432309A GB844574A GB844574A GB1432309A GB 1432309 A GB1432309 A GB 1432309A GB 844574 A GB844574 A GB 844574A GB 844574 A GB844574 A GB 844574A GB 1432309 A GB1432309 A GB 1432309A
Authority
GB
United Kingdom
Prior art keywords
substrate
resistivity
implanted
igfet
mode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB844574A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Signetics Corp
Original Assignee
Signetics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Signetics Corp filed Critical Signetics Corp
Publication of GB1432309A publication Critical patent/GB1432309A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/105—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with vertical doping variation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

1432309 Semiconductor devices SIGNETICS CORP 25 Feb 1974 [2 March 1973] 8445/74 Heading H1K An enhancement-mode IGFET having a gate electrode of a semiconductor material such as polycrystalline silicon has a relatively low resistivity channel region formed, e.g. by ion inplantation, at the surface of a higher resistivity substrate. A process is described which uses conventional planar techniques in the manufacture of such an IGFET in a P-type substrate having a resistivity of 25 # cm. Prior to diffusion of the source and drain regions, e.g. from P-doped glass, the substrate area which the device is to occupy is subjected to B-ion bombardment through an oxide coating under conditions such that the peak density of implanted ions occurs at the substrate surface. The temperature of 700-1000‹ C. employed during the subsequent deposition of the polycrystalline Si gate electrodeissufficiently high to anneal bombardment-produced radiation damage but too low to cause significant migration of implanted ions into the bulk of the substrate. The device may be surrounded by a diffused or implanted P<SP>+</SP> isolation region. The invention is applicable to integrated circuits including both enhancement mode and depletion mode IGFETs, the latter differing from the former only in that the surface implantation of B-ions is omitted. Reference has been directed by the Comptroller to Specification 1,261,723.
GB844574A 1973-03-02 1974-02-25 Semiconductor structures Expired GB1432309A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US33758873A 1973-03-02 1973-03-02

Publications (1)

Publication Number Publication Date
GB1432309A true GB1432309A (en) 1976-04-14

Family

ID=23321143

Family Applications (1)

Application Number Title Priority Date Filing Date
GB844574A Expired GB1432309A (en) 1973-03-02 1974-02-25 Semiconductor structures

Country Status (7)

Country Link
JP (1) JPS5048880A (en)
CA (1) CA1010154A (en)
DE (1) DE2409899A1 (en)
FR (1) FR2220098A1 (en)
GB (1) GB1432309A (en)
IT (1) IT1007410B (en)
NL (1) NL7402828A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2518315A1 (en) * 1981-12-10 1983-06-17 Philips Nv METHOD FOR FORMATION OF AREAS IMPLANTED BY SELF-ALIGNED IONS WITH SUPERPOSED INSULATING LAYER PARTS
GB2123605A (en) * 1982-06-22 1984-02-01 Standard Microsyst Smc MOS integrated circuit structure and method for its fabrication
GB2199694A (en) * 1986-12-23 1988-07-13 Philips Electronic Associated A method of manufacturing a semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2518315A1 (en) * 1981-12-10 1983-06-17 Philips Nv METHOD FOR FORMATION OF AREAS IMPLANTED BY SELF-ALIGNED IONS WITH SUPERPOSED INSULATING LAYER PARTS
GB2123605A (en) * 1982-06-22 1984-02-01 Standard Microsyst Smc MOS integrated circuit structure and method for its fabrication
GB2199694A (en) * 1986-12-23 1988-07-13 Philips Electronic Associated A method of manufacturing a semiconductor device

Also Published As

Publication number Publication date
JPS5048880A (en) 1975-05-01
NL7402828A (en) 1974-09-04
CA1010154A (en) 1977-05-10
FR2220098A1 (en) 1974-09-27
IT1007410B (en) 1976-10-30
DE2409899A1 (en) 1974-09-12

Similar Documents

Publication Publication Date Title
GB1454237A (en) Method for manufacturing a semiconductor device
JPS6446981A (en) Semiconductor device
JPS55113359A (en) Semiconductor integrated circuit device
GB1261723A (en) Improvements in and relating to semiconductor devices
US4797721A (en) Radiation hardened semiconductor device and method of making the same
US4596068A (en) Process for minimizing boron depletion in N-channel FET at the silicon-silicon oxide interface
TW292428B (en) Method for fabricating metal oxide semiconductor
GB1456750A (en) Field effect transistors
JPS57196573A (en) Manufacture of mos type semiconductor device
CA1130473A (en) Mosfet substrate sensitivity control
US4713329A (en) Well mask for CMOS process
GB1316442A (en) Semiconductor devices
DE3561680D1 (en) Method of producing highly integrated mos field-effect transistors
US4362574A (en) Integrated circuit and manufacturing method
JPS5333074A (en) Production of complementary type insulated gate field effect semiconductor device
GB1432309A (en) Semiconductor structures
US4958204A (en) Junction field-effect transistor with a novel gate
YU111284A (en) Process for making semiconductor devices
US3979765A (en) Silicon gate MOS device and method
JPS55134929A (en) Ion implantation
GB1460489A (en) Field-effect transistors
JPS55166958A (en) Manufacture of semiconductor device
JPH04251939A (en) Semiconductor device and manufacture thereof
JPS56107552A (en) Manufacture of semiconductor device
JPS6348865A (en) Semiconductor device

Legal Events

Date Code Title Description
PS Patent sealed
PCNP Patent ceased through non-payment of renewal fee