GB1422586A - Integrated circuits - Google Patents

Integrated circuits

Info

Publication number
GB1422586A
GB1422586A GB2620873A GB2620873A GB1422586A GB 1422586 A GB1422586 A GB 1422586A GB 2620873 A GB2620873 A GB 2620873A GB 2620873 A GB2620873 A GB 2620873A GB 1422586 A GB1422586 A GB 1422586A
Authority
GB
United Kingdom
Prior art keywords
epitaxial layer
barriers
polycrystalline
oxide
ward
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB2620873A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of GB1422586A publication Critical patent/GB1422586A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Memories (AREA)

Abstract

1422586 Integrated circuits INTERNATIONAL BUSINESS MACHINES CORP 1 June 1973 [30 June 1972] 26208/73 Heading H1K Laterial isolation of surface-leakage sensitive semiconductor circuit elements in an integrated circuit is effected by insulating barriers 18 extending through a P--type epitaxial layer 11 and into a P<SP>+</SP>-type substrate 10, the substrate 10 providing a common terminal for all the circuit elements. For a Si structure the barriers 18 are preferably of SiO 2 formed by selectively oxidizing part of the thickness of the epitaxial layer 11, etching the oxide so formed to provide grooves and oxidizing the material exposed in the grooves. The upper surface of the barriers 18 is preferably flush with that of the epitaxial layer 11. Amonst the devices which can employ this form of isolation are charge-coupled devices, field-induced capacitors, dynamic storage cells and dynamic logic cells using FETs. Fig. 11 (not shown) illustrates a pair of IGFETs, one having a metal gate (34) and the other a polycrystalline Si gate (19), located in adjacent islands of the epitaxial layer (11) and separated by an oxide barrier (18). Fig. 12 shows an IGFET having four channel regions 44, 43, 45, 47 in series, each beneath a corresponding gate electrode of which the first and third 42, 46 are of metal and the second and fourth 19 are of polycrystalline Si. Diffused source and drain regions 40, 41 abut the oxide barriers 18. Fig. 10 shows two adjacent memory cells in a memory array provided with diffused N<SP>+</SP>-type bit lines adjacent isolation barriers 18, and orthogonal Al ward lines 27. Each cell includes an IGFET constituted by a bit line 22 as source, a channel region 23 of the epitaxial layer 11, a Si 3 N 4 -on-SiO 2 gate insulation 16 and part of the ward line 27 as gate electrode. Charge conducted through the channel region 23 is stored in a capacitor constituted by a polycrystalline Si electrode 19, part of the insulation 16 and the underlying area 20 of the epitaxial layer 11. The polycrystalline Si electrode 19 is separated from the overlying Al ward line 27 by an oxide layer 24, and a similar layer isolates the ward line 27 from each bit line 22 except where contact is required to be made. The capacitor electrodes 19 may alternatively be made of a refractory metal. A method of manufacture using conventional planar processing steps is described.
GB2620873A 1972-06-30 1973-06-01 Integrated circuits Expired GB1422586A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US26777172A 1972-06-30 1972-06-30

Publications (1)

Publication Number Publication Date
GB1422586A true GB1422586A (en) 1976-01-28

Family

ID=23020055

Family Applications (1)

Application Number Title Priority Date Filing Date
GB2620873A Expired GB1422586A (en) 1972-06-30 1973-06-01 Integrated circuits

Country Status (6)

Country Link
JP (1) JPS528229B2 (en)
CA (1) CA1005925A (en)
DE (1) DE2318912A1 (en)
FR (1) FR2191270B1 (en)
GB (1) GB1422586A (en)
IT (1) IT987426B (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2554450A1 (en) * 1975-12-03 1977-06-16 Siemens Ag Integrated circuit prodn. with FET in silicon substrate - with polycrystalline silicon gate electrode and planar insulating oxide film
DE2720533A1 (en) * 1977-05-06 1978-11-09 Siemens Ag MONOLITHIC INTEGRATED CIRCUIT ARRANGEMENT WITH SINGLE TRANSISTOR STORAGE ELEMENTS
CA1186808A (en) * 1981-11-06 1985-05-07 Sidney I. Soclof Method of fabrication of dielectrically isolated cmos device with an isolated slot
JPS58100441A (en) * 1981-12-10 1983-06-15 Toshiba Corp Manufacture of semiconductor device
JPS58212165A (en) * 1983-05-23 1983-12-09 Nec Corp Semiconductor device
JPH0616549B2 (en) * 1984-04-17 1994-03-02 三菱電機株式会社 Semiconductor integrated circuit device
JP2003124514A (en) * 2001-10-17 2003-04-25 Sony Corp Semiconductor light emitting element and its manufacturing method

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL153374B (en) * 1966-10-05 1977-05-16 Philips Nv PROCESS FOR THE MANUFACTURE OF A SEMICONDUCTOR DEVICE PROVIDED WITH AN OXIDE LAYER AND SEMI-CONDUCTOR DEVICE MANUFACTURED ACCORDING TO THE PROCEDURE.
FR2079612A5 (en) * 1970-02-06 1971-11-12 Radiotechnique Compelec
US3698966A (en) * 1970-02-26 1972-10-17 North American Rockwell Processes using a masking layer for producing field effect devices having oxide isolation
US3859717A (en) * 1970-12-21 1975-01-14 Rockwell International Corp Method of manufacturing control electrodes for charge coupled circuits and the like
US3751722A (en) * 1971-04-30 1973-08-07 Standard Microsyst Smc Mos integrated circuit with substrate containing selectively formed resistivity regions

Also Published As

Publication number Publication date
FR2191270B1 (en) 1977-07-29
FR2191270A1 (en) 1974-02-01
JPS4945688A (en) 1974-05-01
IT987426B (en) 1975-02-20
DE2318912A1 (en) 1974-01-17
CA1005925A (en) 1977-02-22
JPS528229B2 (en) 1977-03-08

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Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
PCNP Patent ceased through non-payment of renewal fee