GB1419970A - Field effect transistor memory circuits - Google Patents
Field effect transistor memory circuitsInfo
- Publication number
- GB1419970A GB1419970A GB5989872A GB5989872A GB1419970A GB 1419970 A GB1419970 A GB 1419970A GB 5989872 A GB5989872 A GB 5989872A GB 5989872 A GB5989872 A GB 5989872A GB 1419970 A GB1419970 A GB 1419970A
- Authority
- GB
- United Kingdom
- Prior art keywords
- threshold
- read signal
- turned
- select
- read
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Non-Volatile Memory (AREA)
- Read Only Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
1419970 FET data stores SONY CORP 28 Dec 1972 [29 Dec 1971] 59898/72 Heading H3T A variable threshold F.E.T. 2, 5, 8 or 11 can be set/reset by a single input terminal R/W only when its source is earthed through an X- selection F.E.T. 1, 4, 7 or 10 and a Y-selection F.E.T. 17 or 18. The arrangement is said to require the necessary high voltages for threshold-setting to be applied to only one terminal (i.e. R/W), permitting the memory and addressing F.E.T.s to be formed on a single chip. If for example F.E.T.s 1 and 17 are turned on by X1, Y1 then F.E.T. 2 can have its threshold set to the high state (1) by +40 volts at R/W, this state requiring a gate voltage of + 15 v. (Fig. 4, not shown) to make F.E.T. 2 conduct during a subsequent read period. Thus a + 10 v. read signal at R/W produces conduction of F.E.T. 2 only if the low threshold exists (0). To reset the low threshold, R/W goes to - 40 v. while X1 and Y1 select F.E.T. 2, and while another F.E.T. 13 is turned on by an erase signal E to earth the drain of F.E.T. 2. Conduction of F.E.T. 2 during reading is detected at R OUT <SP>1</SP>, and similarly for F.E.T. 5. For F.E.T.s 8 and 11, readout to R OUT <SP>1</SP> requires gating F.E.T.s 15 and 16 to be turned on by a read signal R. In one modification, a single load F.E.T. 3,6 (Fig. 5, not shown) is used for each column, being connected to each cell by extra gating F.E.T.s (31, 32; 35, 36; &c.) controlled by complements of the X, Y signals and by the read signal R. In another modification (Fig. 7, not shown), the erase and read F.E.T.s 14, 15, 16 are removed, the X select F.E.T.s 1, 4, 7, 10 and their respective variable threshold F.E.T.s 2, 5, 8, 11 exchange positions, and the Y select F.E.T.s 17, 18 are connected to receive the read signal R instead of earth. The variable threshold F.E.T.s may use silicon nitride, or aluminium oxide, between the gate and the silicon oxide layer.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP133572A JPS568438B2 (en) | 1971-12-29 | 1971-12-29 |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1419970A true GB1419970A (en) | 1975-12-31 |
Family
ID=11498613
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB5989872A Expired GB1419970A (en) | 1971-12-29 | 1972-12-28 | Field effect transistor memory circuits |
Country Status (5)
Country | Link |
---|---|
JP (1) | JPS568438B2 (en) |
CA (1) | CA986223A (en) |
DE (1) | DE2264067A1 (en) |
GB (1) | GB1419970A (en) |
NL (1) | NL7217793A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP2988331A1 (en) * | 2000-08-14 | 2016-02-24 | SanDisk 3D LLC | Semiconductor memory device |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS50134739A (en) * | 1974-04-15 | 1975-10-25 | ||
JPS5443634A (en) * | 1977-09-13 | 1979-04-06 | Nippon Telegr & Teleph Corp <Ntt> | Memory erasing method |
-
1971
- 1971-12-29 JP JP133572A patent/JPS568438B2/ja not_active Expired
-
1972
- 1972-12-28 CA CA160,103A patent/CA986223A/en not_active Expired
- 1972-12-28 GB GB5989872A patent/GB1419970A/en not_active Expired
- 1972-12-29 DE DE19722264067 patent/DE2264067A1/en not_active Ceased
- 1972-12-29 NL NL7217793A patent/NL7217793A/xx not_active Application Discontinuation
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP2988331A1 (en) * | 2000-08-14 | 2016-02-24 | SanDisk 3D LLC | Semiconductor memory device |
US9559110B2 (en) | 2000-08-14 | 2017-01-31 | Sandisk Technologies Llc | Dense arrays and charge storage devices |
US10008511B2 (en) | 2000-08-14 | 2018-06-26 | Sandisk Technologies Llc | Dense arrays and charge storage devices |
US10644021B2 (en) | 2000-08-14 | 2020-05-05 | Sandisk Technologies Llc | Dense arrays and charge storage devices |
Also Published As
Publication number | Publication date |
---|---|
DE2264067A1 (en) | 1973-07-05 |
NL7217793A (en) | 1973-07-03 |
CA986223A (en) | 1976-03-23 |
JPS568438B2 (en) | 1981-02-24 |
JPS4874128A (en) | 1973-10-05 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed | ||
PCNP | Patent ceased through non-payment of renewal fee |