GB1412785A - Graphic display system - Google Patents
Graphic display systemInfo
- Publication number
- GB1412785A GB1412785A GB5741172A GB5741172A GB1412785A GB 1412785 A GB1412785 A GB 1412785A GB 5741172 A GB5741172 A GB 5741172A GB 5741172 A GB5741172 A GB 5741172A GB 1412785 A GB1412785 A GB 1412785A
- Authority
- GB
- United Kingdom
- Prior art keywords
- memory
- matrix
- data
- rewrite
- line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000015654 memory Effects 0.000 abstract 15
- 239000011159 matrix material Substances 0.000 abstract 9
- 230000002441 reversible effect Effects 0.000 abstract 4
- 230000006870 function Effects 0.000 abstract 3
- 230000003134 recirculating effect Effects 0.000 abstract 3
- 230000008030 elimination Effects 0.000 abstract 1
- 238000003379 elimination reaction Methods 0.000 abstract 1
- 238000012840 feeding operation Methods 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
- G09G5/39—Control of the bit-mapped memory
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
- G09G5/363—Graphics controllers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Controls And Circuits For Display Device (AREA)
- Image Generation (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
1412785 Cathode-ray tube displays TOKYO SHIBAURA ELECTRIC CO Ltd 13 Dec 1972 [14 Dec 1971] 57411/72 Heading H4T In a cathode-ray tube graphic display system in which the display is produced by intensity modulation of the beam as it is scanned line rasterwise, a control circuit 14 (Fig. 1), on command of a computer 13, causes a function generator 15 to produce data (digital numbers) representative of the X and Y co-ordinates of successive points on, e.g. a line, of a figure to be displayed, such data being stored in a matrix memory 16 from which it is supplied to a rewrite memory 17 the output of which intensity modulates the beam of the display tube 11 as it is scanned in line raster fashion under the control of the read out of data from the rewrite memory 17. A further rewrite memory 18 may supply a further display tube 12 located remotely from tube 11 and matrix 16 may supply memories 17, 18 alternately, with different data. The function generator 15 comprises respective X-axis and Y-axis co-ordinate registers in which the co-ordinates are set, together with sign bits, as binary numbers by means of the control circuit 14 which then operates to read out these numbers serially and supply the outputs to respective reversible X and Y registers in which the initial positions have been already set (Fig. 2, not shown). The memory matrix 16, comprises 512 rows of integrated circuits each having 512 addresses at which, under the control of the reversible X and Y registers of the function generator, the successive points forming the line are set up, appropriately spatially arranged. When this has been done the X-axis reversible register is disabled and the Y-axis reversible counter is then employed to read-out successive " horizontal lines " of the matrix into a series of flipflops (Fig. 3, not shown). The rewrite memory comprises a store including 512 rows of MOS integrated circuit recirculating shift registers corresponding respectively to the individual lines of the display each having a bit capacity equal to the maximum line resolution (512) plus the fly-back time of the beam, successive registers being loaded serially by means of the series of flip-flops associated with the memory matrix and then read out in the same order and supplied to the beam intensity control electrode synchronously with the line scanning (Fig. 4, not shown). In order to reduce cost the memory matrix may have a capacity of one quarter that of the rewrite memory store, the latter being divided into four sections of 256 x 256 bit capacity fed successively from the matrix memory which receives new data after each feeding operation. A partial addition to the displayed figure may be made by writing the additional data in the matrix memory, after the main figure data has been transferred and transferring this to the rewrite memory via an OR gate in the recirculating loop of the latter (Fig. 5, not shown) and a partial elimination of the main figure may be effected by writing data relating to such part into the memory matrix and transferring it via an AND gate in the recirculating loop of the rewrite memory (Fig. 6, not shown).
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP46101628A JPS5134257B2 (en) | 1971-12-14 | 1971-12-14 |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1412785A true GB1412785A (en) | 1975-11-05 |
Family
ID=14305653
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB5741172A Expired GB1412785A (en) | 1971-12-14 | 1972-12-13 | Graphic display system |
Country Status (4)
Country | Link |
---|---|
US (1) | US3836902A (en) |
JP (1) | JPS5134257B2 (en) |
DE (1) | DE2261141C3 (en) |
GB (1) | GB1412785A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2148077A (en) * | 1983-09-20 | 1985-05-22 | Rees Elwyn | Video display control system |
US4638422A (en) * | 1983-05-19 | 1987-01-20 | Elwyn Rees | Data entry interface assembly |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3973245A (en) * | 1974-06-10 | 1976-08-03 | International Business Machines Corporation | Method and apparatus for point plotting of graphical data from a coded source into a buffer and for rearranging that data for supply to a raster responsive device |
US4026555A (en) * | 1975-03-12 | 1977-05-31 | Alpex Computer Corporation | Television display control apparatus |
DE2449886B1 (en) * | 1975-05-30 | 1975-12-18 | Elliott Brothers London Ltd | Television camera |
US4028724A (en) * | 1975-11-10 | 1977-06-07 | Rca Corporation | Read/write character generator memory loading method |
US4069511A (en) * | 1976-06-01 | 1978-01-17 | Raytheon Company | Digital bit image memory system |
US4119955A (en) * | 1977-03-24 | 1978-10-10 | Intel Corporation | Circuit for display, such as video game display |
JPS54824A (en) * | 1977-06-03 | 1979-01-06 | Fujitsu Ltd | Writing control system for ruled line data |
US4208723A (en) * | 1977-11-28 | 1980-06-17 | Gould Inc. | Data point connection circuitry for use in display devices |
FR2426296A1 (en) * | 1978-05-18 | 1979-12-14 | Thomson Csf | VECTOR GENERATOR FOR GRAPHIC CONSOLE |
IT1108410B (en) * | 1978-09-25 | 1985-12-09 | Indesit | TELEVISION |
US4222108A (en) * | 1978-12-01 | 1980-09-09 | Braaten Norman J | Digitally-programmed arbitrary waveform generator |
JPS5576437A (en) * | 1978-12-04 | 1980-06-09 | Hitachi Ltd | Graphic display unit |
JPS57500529A (en) * | 1980-02-29 | 1982-03-25 | ||
JPS5794784A (en) * | 1980-11-20 | 1982-06-12 | Kobe Steel Ltd | Picture information synthetizing terminal |
US4482979A (en) * | 1982-02-04 | 1984-11-13 | May George A | Video computing system with automatically refreshed memory |
CA1243138A (en) * | 1984-03-09 | 1988-10-11 | Masahiro Kodama | High speed memory access circuit of crt display unit |
US4884069A (en) * | 1987-03-19 | 1989-11-28 | Apple Computer, Inc. | Video apparatus employing VRAMs |
US5668577A (en) * | 1994-08-12 | 1997-09-16 | Sutter; Erich E. | Video circuit for generating special fast dynamic displays |
US6025829A (en) * | 1996-10-28 | 2000-02-15 | Welch Allyn, Inc. | Image generator for video display |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3179883A (en) * | 1960-11-08 | 1965-04-20 | Bell Telephone Labor Inc | Point matrix display unit for testing logic circuit |
US3396377A (en) * | 1964-06-29 | 1968-08-06 | Gen Electric | Display data processor |
US3422420A (en) * | 1966-03-23 | 1969-01-14 | Rca Corp | Display systems |
-
1971
- 1971-12-14 JP JP46101628A patent/JPS5134257B2/ja not_active Expired
-
1972
- 1972-12-13 GB GB5741172A patent/GB1412785A/en not_active Expired
- 1972-12-14 DE DE2261141A patent/DE2261141C3/en not_active Expired
- 1972-12-14 US US00315012A patent/US3836902A/en not_active Expired - Lifetime
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4638422A (en) * | 1983-05-19 | 1987-01-20 | Elwyn Rees | Data entry interface assembly |
GB2148077A (en) * | 1983-09-20 | 1985-05-22 | Rees Elwyn | Video display control system |
Also Published As
Publication number | Publication date |
---|---|
JPS5134257B2 (en) | 1976-09-25 |
JPS4866333A (en) | 1973-09-11 |
DE2261141A1 (en) | 1973-06-20 |
DE2261141C3 (en) | 1978-05-03 |
DE2261141B2 (en) | 1977-09-29 |
US3836902A (en) | 1974-09-17 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed [section 19, patents act 1949] | ||
PCNP | Patent ceased through non-payment of renewal fee |