GB1397271A - Bidirectional data shift unit - Google Patents

Abstract

1397271 Shift network INTERNATIONAL BUSINESS MACHINES CORP 14 July 1972 [14 Aug 1971] 32965/72 Heading G4A A bidirectional data shift unit includes a number of cascaded shift levels each arranged in response to control signals to shift a group of binary bits by different amounts, a number of overflow indicator circuits associated with respective ones of the shift levels and arranged to generate an output in response to the shift control signals associated with their associated level and those bits supplied to their associated level which may overflow as a result of a shift in that level, and a logic circuit responsive to the signals from the indicator circuits and a parity bit for the group of bits originally supplied to the shift unit to generate a parity bit for the shifted output produced by the unit. In an embodiment the unit includes three levels I, II and III arranged to shift an input group of bits by no bit positions or by one, two and four bit positions respectively to the right or left. Each level consists of AND gates enabled by control signals and fed with bits from the previous level (or the input), the position of the bit supplied to any gate relative to the position of the gate being determined by the degree of shift induced by that gate. Associated with each level is an overflow indicator circuit 36, 37, 38 which receives the shift control signals for the associated level and consists of AND gates fed with the bits which are supplied to the associated level and which may overflow as a result of a shift in that level, and the control signal which produces the particular shifts producing the overflows. The outputs of the indicator circuits are fed together with the parity bit of the original group of bits to a tree of exclusive OR gates. The output of the tree is a parity bit for the shifted output of the device. In a second embodiment arranged to shift a two byte, 16 bit input group, each byte having an associated parity bit, the first level is arranged to shift right or left by eight bit positions or to pass the input unshifted. Three lower levels are the same as in the first embodiment above. The indicator circuit associated with the first level consists of two AND gates fed with the shift control signals and the two byte parity bits, and an exclusive OR gate fed with the two byte parity bits. An exclusive OR tree is provided to generate a single parity bit for the 16 bit shifted output group. The output of an exclusive OR tree for generating a parity bit for one of the output bytes is fed together with the single parity bit to an exclusive OR gate to produce a parity bit for the other output byte. The parity generated for the shifted output may be compared with a parity bit generated from the shifted output for error detection purposes.