GB1373940A - Data transmission systems - Google Patents

Abstract

1373940 Facsimile communication bandwidth reduction; digital transmission coding RICOH KK 30 Dec 1971 [31 Dec 1970] 60656/71 Headings H4F and H4P In a system for transmitting signals representing successive data groups'containing equal numbers of bits, each data group is compared with the preceding one and if the similarity between them is less than a predetermined degree the new group is transmitted in its entirety, whereas if the similarity is greater than the predetermined degree signals representing the differences between the groups compared are transmitted. Preferably, if the groups are identical a first code signal is transmitted and if they are similar but not identical a second code signal is transmitted followed by address signals of the bits which are different. Signals produced by raster-scanning of a picture are binary coded and supplied on line 302 to a data compressor, Fig. 3. Upon completion of a scanning line a sync. signal is supplied to control circuit 300 to set the compressor to a MODE I condition in which AND- gate G1 is enabled and the bit pattern of the line just scanned is fed into shift register 303. The bit pattern of the previous line is already stored in register 304. The compressor is then set to a MODE 2 condition by control circuit 300, in which condition gates G2, G4 and G7 are enabled and a shift pulse causes the contents of the two shift registers to be circulated through lines 306 and 308. A comparator 309 compares the two signal trains and generates a "1" signal in response to non-identical bits, the output from the comparator being fed to a counter 310. When circulation is complete the compressor is switched to MODE 3 in which the count in counter 310 is decoded by discriminator 311. If the count is zero (identical bit patterns in registers 303, 304) a "1" appears on line 312. If the count lies between 1 and a predetermined number, such as 64 (similar but not identical bit patterns) a 1 is produced on line 313, and if the count is above 64 (dissimilar patterns) a 1 is produced on line 314. In response to signals on lines 312, 313 and 314 encoder 315 generates EQL, ANL and NEW signals, respectively, for storage in buffer memory 320. The compressor is now set to MODE 4 in which the contents of shift register 303 are shifted into register 304. In addition, if a "1" signal is present on line 313 gate G8 is enabled and counter 317 is supplied with clock pulses in synchronism with the shift pulses supplied to registers 303 and 304. Comparator 309 again compares the contents of the registers and generates a "1" signal for non- identical bits. These signals, which represent the addresses of bits which are to be changed, are passed to counter 317 which produces a corresponding output on line 318 for storage in buffer memory 320. When the contents of 303 and 304 have been completely shifted the compressor is switched to MODE 5. If, in MODE 4, a signal is present on line 314, instead of 313, AND gate G9 is enabled, instead of G8, and the new bit pattern from register 303 is passed directly to the buffer memory. If a signal is present on line 312 only the transfer of the contents of register 303 to 304 occurs in MODE 4. In MODE 5 the contents of buffer memory 320 are transferred through output line 321 to a transmission modem, and will consist of an EQL signal, or an ANL signal followed by the addresses of non-identical bits, or a NEW signal followed by the new bit pattern. In the receiver received signals are demodulated by a reception modem and supplied to an expander, Fig. 4. Shift register 409 contains the bit pattern of the last received line. Newly received signals are stored in buffer memory 402 and applied to decoder 404 which produces an output on line 405, 406, 407 depending on which of the signals EQL, ANL or NEW is present. In response to an EQL signal gates G10 and G14 are enabled and the contents of shift register 409 are shifted to output line 417 and are also recirculated through line 410. When a NEW signal is received gate G11 is enabled and the new bit pattern is stored in register 409, after which gates G10 and G14 are enabled to transfer to new pattern to the output line and to recirculate it. In response to an ANL signal the first address signal is supplied to comparator 412 and counter 413 is simultaneously actuated. At the same time the contents of register 409 are shifted. As long as the received address signal is not identical with the content of counter 413 a zero output is present on line 414, but this changes to a "1" when the signals are identical. While line 414 carries zero output gate G10 alone is enabled. When a "1" is produced gate G12 alone is enabled and the register output is inverted before being recirculated. Finally gates G10 and G14 are enabled to supply the newly-formed bit pattern to the output line and recirculate it. The code signals EQL, ANL and NEW and the address signals may consist of up to ten bits. The code signals for EQL and ANL may be the same, the former being followed by allzero address signals.