GB1362345A - Semiconductor device manufacture - Google Patents
Semiconductor device manufactureInfo
- Publication number
- GB1362345A GB1362345A GB3403572A GB3403572A GB1362345A GB 1362345 A GB1362345 A GB 1362345A GB 3403572 A GB3403572 A GB 3403572A GB 3403572 A GB3403572 A GB 3403572A GB 1362345 A GB1362345 A GB 1362345A
- Authority
- GB
- United Kingdom
- Prior art keywords
- region
- base
- oxide
- etching
- contact
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000004519 manufacturing process Methods 0.000 title abstract 2
- 239000004065 semiconductor Substances 0.000 title 1
- 238000005530 etching Methods 0.000 abstract 6
- 150000002500 ions Chemical class 0.000 abstract 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 3
- 230000000873 masking effect Effects 0.000 abstract 3
- 229920002120 photoresistant polymer Polymers 0.000 abstract 3
- 229910052710 silicon Inorganic materials 0.000 abstract 3
- 239000010703 silicon Substances 0.000 abstract 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 238000000151 deposition Methods 0.000 abstract 2
- 238000009792 diffusion process Methods 0.000 abstract 2
- 238000002513 implantation Methods 0.000 abstract 2
- 238000005468 ion implantation Methods 0.000 abstract 2
- 239000000758 substrate Substances 0.000 abstract 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract 1
- 239000004411 aluminium Substances 0.000 abstract 1
- 229910052782 aluminium Inorganic materials 0.000 abstract 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract 1
- 238000000137 annealing Methods 0.000 abstract 1
- 229910052796 boron Inorganic materials 0.000 abstract 1
- -1 boron ions Chemical class 0.000 abstract 1
- 230000000694 effects Effects 0.000 abstract 1
- 229910052751 metal Inorganic materials 0.000 abstract 1
- 239000002184 metal Substances 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 238000012986 modification Methods 0.000 abstract 1
- 230000004048 modification Effects 0.000 abstract 1
- 230000002093 peripheral effect Effects 0.000 abstract 1
- 229910052698 phosphorus Inorganic materials 0.000 abstract 1
- 239000011574 phosphorus Substances 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
- H01L21/2652—Through-implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- High Energy & Nuclear Physics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Bipolar Transistors (AREA)
Abstract
1362345 Manufacture of inverted bipolar transistors MULLARD Ltd 11 May 1973 [20 July 1972] 34035/72 Heading H1K In making the base region of an inverted bipolar transistor by ion implantation through a surface masking layer into a layer of one conductivity type on a higher conductivity region of the same type, the portion of the masking layer immediately adjacent the window is constructed to be semi-permeable to the ions to provide a peripheral region of the base in which the ions are less deeply implanted, while the ions in the unmasked region extend to the higher conductivity region. The described processes start with an epitaxial N layer on an N + silicon substrate which ultimately constitutes the emitter zone. Thick oxide is thermally grown over the layer, apertured by photolithographic and etching steps, a thinner oxide regrown in the aperture and similarly apertured at one side, the etching being such that the apertures have chamfered edges. Bombardment with 500 keV boron ions produces a base zone which extends to the surface under the thin oxide to form a contact region and under the chamfered edge, and an unconverted N-type collector region at the exposed silicon surface. The base contact region may alternatively be formed in a separate diffusion or implantation step. After annealing at 700 C. and optionally providing a collector contact region by diffusion or implantation a base contact hole is etched and aluminium deposited and pattern etched to form the base and collector electrodes, and an emitter contact provided on the back of the wafer. In a modification for integrated circuit use the N+ silicon is a diffused inclusion in a P-type substrate and an emitter electrode provided on the upper face contacts the inclusion via a connecting region. In a further variant the ion energy is such that the base zone extends also to the exposed surface, on which a Schottky collector electrode is provided. The mask aperture may alternatively be provided with a stepped edge either by depositing silica on or diffusing phosphorus into the surface of the grown oxide to provide a faster etching layer to increase undercutting of the photoresist etching mask. A similar effect is obtained by depositing metal over the oxide, using it to mask preferential etching of the oxide and then preferentially etching it to undercut the overlying photoresist mask. In another embodiment, Fig. 7, after aperturing the thick oxide, very thin oxide is regrown in the aperture, itself apertured centrally, and a base contact 32 deposited in the aperture. A photoresist mask 33 after development is baked so that it plastically flows to produce graded edges 6 and ion implantation effected as before but with the partial masking effect of the contact 32 providing a self registered contact region. Electrodes are then provided substantially as above. Reference has been directed by the Comptroller to Specification 1,294,515.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB3403572A GB1362345A (en) | 1973-05-11 | 1973-05-11 | Semiconductor device manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB3403572A GB1362345A (en) | 1973-05-11 | 1973-05-11 | Semiconductor device manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB1362345A true GB1362345A (en) | 1974-08-07 |
Family
ID=10360554
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB3403572A Expired GB1362345A (en) | 1973-05-11 | 1973-05-11 | Semiconductor device manufacture |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB1362345A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2389234A1 (en) * | 1977-04-29 | 1978-11-24 | Ibm | PROCESS FOR MANUFACTURING SEMICONDUCTOR DEVICES IN INTEGRATED INJECTION LOGIC (IIL) AND RESULTING DEVICES |
| EP0002191A1 (en) * | 1977-11-30 | 1979-06-13 | International Business Machines Corporation | Integrated semiconductor device in I2L-technique and method of manufacturing it |
| US4202002A (en) * | 1977-01-19 | 1980-05-06 | International Business Machines Corporation | Ion-implanted layers with abrupt edges |
| EP0080523A1 (en) * | 1981-11-28 | 1983-06-08 | Deutsche ITT Industries GmbH | Process for producing a monolithic integrated circuit having at least one pair of complementary field-effect transistors and at least one bipolar transistor |
| GB2183905A (en) * | 1985-11-18 | 1987-06-10 | Plessey Co Plc | Semiconductor device manufacture |
| EP1035566A2 (en) * | 1999-03-03 | 2000-09-13 | Infineon Technologies North America Corp. | Method for forming a buried doped layer with connecting portions within a semiconductive device |
-
1973
- 1973-05-11 GB GB3403572A patent/GB1362345A/en not_active Expired
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4202002A (en) * | 1977-01-19 | 1980-05-06 | International Business Machines Corporation | Ion-implanted layers with abrupt edges |
| FR2389234A1 (en) * | 1977-04-29 | 1978-11-24 | Ibm | PROCESS FOR MANUFACTURING SEMICONDUCTOR DEVICES IN INTEGRATED INJECTION LOGIC (IIL) AND RESULTING DEVICES |
| EP0002191A1 (en) * | 1977-11-30 | 1979-06-13 | International Business Machines Corporation | Integrated semiconductor device in I2L-technique and method of manufacturing it |
| EP0080523A1 (en) * | 1981-11-28 | 1983-06-08 | Deutsche ITT Industries GmbH | Process for producing a monolithic integrated circuit having at least one pair of complementary field-effect transistors and at least one bipolar transistor |
| GB2183905A (en) * | 1985-11-18 | 1987-06-10 | Plessey Co Plc | Semiconductor device manufacture |
| GB2183905B (en) * | 1985-11-18 | 1989-10-04 | Plessey Co Plc | Method of semiconductor device manufacture |
| EP1035566A2 (en) * | 1999-03-03 | 2000-09-13 | Infineon Technologies North America Corp. | Method for forming a buried doped layer with connecting portions within a semiconductive device |
| EP1035566A3 (en) * | 1999-03-03 | 2000-10-04 | Infineon Technologies North America Corp. | Method for forming a buried doped layer with connecting portions within a semiconductive device |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PS | Patent sealed [section 19, patents act 1949] | ||
| PLNP | Patent lapsed through nonpayment of renewal fees |