GB1362314A - Method for programming a computer to simulate a digital circuit - Google Patents

Abstract

1362314 Data processing; diagnostic programs INTERNATIONAL BUSINESS MACHINES CORP 8 Aug 1972 36916/72 Heading G4A A fault simulation technique used in diagnostic programs for digital computers is disclosed. Fault simulation is used to determine the coverage and resolution of the diagnostic (i.e. the numbers of failures detected and their distinguishing level), to improve the diagnostic program and to prepare the failure documentation for the customer engineer. The described technique simulates only those logic circuits that might be affected by a given set of input changes (significant event simulation). Initially test patterns 12 and the computer circuit description 13 are fed into a non-failing machine simulation cycle 11a to produce an all events trace (AET) 14 which records the circuit activity on receipt of the test patterns without any failures..Then a fault simulation cycle 11b is entered during which a failure (or a group of failures) is simulated for the logic circuit, the initial effects are propagated, a good machine logic value change is read from the AET and the circuit value table is either updated from this, or if the logic is affected by the fault, fresh values are calculated. The fault affected logic is determined by three flags. The fact that only the fault affected area has its values recalculated is stated to reduce simulation time. The simulation is preferably applied to a three valued (0, 1, don't know) unit delay system.