GB1329582A - Signal translating apparatus - Google Patents

Signal translating apparatus

Info

Publication number
GB1329582A
GB1329582A GB4695070A GB4695070A GB1329582A GB 1329582 A GB1329582 A GB 1329582A GB 4695070 A GB4695070 A GB 4695070A GB 4695070 A GB4695070 A GB 4695070A GB 1329582 A GB1329582 A GB 1329582A
Authority
GB
United Kingdom
Prior art keywords
pulse
gate
line
signal
frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB4695070A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Compteurs Schlumberger SA
Original Assignee
Compteurs Schlumberger SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from FR6933695A external-priority patent/FR2019913A1/fr
Application filed by Compteurs Schlumberger SA filed Critical Compteurs Schlumberger SA
Publication of GB1329582A publication Critical patent/GB1329582A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01P—MEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, DECELERATION, OR SHOCK; INDICATING PRESENCE, ABSENCE, OR DIRECTION, OF MOVEMENT
    • G01P3/00—Measuring linear or angular speed; Measuring differences of linear or angular speeds
    • G01P3/42—Devices characterised by the use of electric or magnetic means
    • G01P3/56—Devices characterised by the use of electric or magnetic means for comparing two speeds
    • G01P3/60—Devices characterised by the use of electric or magnetic means for comparing two speeds by measuring or comparing frequency of generated currents or voltages
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01F—MEASURING VOLUME, VOLUME FLOW, MASS FLOW OR LIQUID LEVEL; METERING BY VOLUME
    • G01F15/00—Details of, or accessories for, apparatus of groups G01F1/00 - G01F13/00 insofar as such details or appliances are not adapted to particular types of such apparatus
    • G01F15/07—Integration to give total flow, e.g. using mechanically-operated integrating mechanism
    • G01F15/075—Integration to give total flow, e.g. using mechanically-operated integrating mechanism using electrically-operated integrating means
    • G01F15/0755—Integration to give total flow, e.g. using mechanically-operated integrating mechanism using electrically-operated integrating means involving digital counting
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Fluid Mechanics (AREA)
  • Investigating Or Analysing Biological Materials (AREA)
  • Magnetic Resonance Imaging Apparatus (AREA)

Abstract

1329582 Pulse signal translating circuits COMPAGNIE DES COMPTEURS 2 Oct 1970 [2 Oct 1969] 46950/70 Heading H3P An arrangement responsive to the relative frequency of two pulse trains E1, E2 comprises: means 10 for deriving from these trains res. pective pulse trains S 1 , S 2 which are separated in time; a gate 15 having a first state in which a first input pulse train S 1 is passed to output F; and means 11, 12 responsive to a first pulse in a second input pulse train S 2 to inhibit the gate 15, and responsive to a succeeding pulse in train S 1 to reopen the gate. If no signal is present at S 2 , bi-stable 11 produces a "1" on line J, and an S 1 pulse is fed via NOR 13 and delay 14 to trigger JK flipflop 12 to a "1" on line Q, which enables NAND gate 15. The S 1 signal is inverted at 16 and the resulting S 1 signal is passed by NAND gate 15 to appear as S 1 at the output F. When a pulse occurs at S 2 , bi-stable 11 is switched to provide a "1" on line K, and the next trigger pulse on line D will switch JK flipflop 12 to "0" on line Q, so inhibiting gate 15. The next S 1 pulse will not therefore be passed by gate 15, but will reset bi-stable 11 to J = 1 so that the next trigger pulse on line D will switch JK flipflop 12 back to Q = 1 and reopen gate 15. If we assume the frequency of S 1 to be greater than that of S 2 , the output at F represents the frequency difference. Similarly if the frequency of S 2 is greater, and elements 161, 15<SP>1</SP> are added, the difference signal appears at F<SP>1</SP>. If a further NAND gate 17 is added, detection of parasitic pulses present in two signals of nominally the same frequency may be detected.
GB4695070A 1969-10-02 1970-10-02 Signal translating apparatus Expired GB1329582A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR6933695A FR2019913A1 (en) 1968-10-04 1969-10-02

Publications (1)

Publication Number Publication Date
GB1329582A true GB1329582A (en) 1973-09-12

Family

ID=9040952

Family Applications (1)

Application Number Title Priority Date Filing Date
GB4695070A Expired GB1329582A (en) 1969-10-02 1970-10-02 Signal translating apparatus

Country Status (1)

Country Link
GB (1) GB1329582A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2313680A1 (en) * 1975-05-31 1976-12-31 Werner & Pfleiderer PROTECTIVE ELECTRICAL CIRCUIT FOR COUPLINGS, IN PARTICULAR FOR ANTI-OVERLOAD COUPLINGS
DE10320793A1 (en) * 2003-04-30 2004-12-16 Infineon Technologies Ag Latch or phase detector circuit for DRAM data storage uses flip flop stage and cascaded NAND gates to give output depending on clock and data state change phase

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2313680A1 (en) * 1975-05-31 1976-12-31 Werner & Pfleiderer PROTECTIVE ELECTRICAL CIRCUIT FOR COUPLINGS, IN PARTICULAR FOR ANTI-OVERLOAD COUPLINGS
DE10320793A1 (en) * 2003-04-30 2004-12-16 Infineon Technologies Ag Latch or phase detector circuit for DRAM data storage uses flip flop stage and cascaded NAND gates to give output depending on clock and data state change phase
DE10320793B4 (en) * 2003-04-30 2005-04-21 Infineon Technologies Ag Latch or phase detector circuit for DRAM data storage uses flip flop stage and cascaded NAND gates to give output depending on clock and data state change phase

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Legal Events

Date Code Title Description
PS Patent sealed
PCNP Patent ceased through non-payment of renewal fee