GB1315690A - Data transfer systems - Google Patents

Abstract

1315690 Data transfer FERRANTI Ltd 23 Nov 1971 [25 Nov 1970] 56008/70 Heading G4H A data transfer system having a plurality of peripheral units any one of which may be required to transmit data to or receive data from other such units, includes at least two independent data highways, a separate controller for each highway operable to transmit over its highway a sequence of control instructions identical to the sequence transmitted by each other controller, synchronizing means included in each controller for maintaining its sequence of control instructions in synchronism with the sequence transmitted by each other controller, separate connections between each highway and each peripheral unit, and checking means included in each peripheral unit operable to check each received control instruction and to cause the unit to act only upon predetermined ones of the instructions. In a flight-aid system, sensors in some peripheral units feed data to a computer in another, which sends control data to transducers in further peripheral units. As disclosed, there are three highways, each having a data line and a clock line. Each bit on the data line is accompanied by a clock pulse on the clock line. Controller.-A control instruction generator (read-only store) provides a control instruction into an output shift register, generated parity, validity and control bits being appended before shift out on to the data line to all the peripheral units. In normal operation, the control instruction is returned by the peripheral units within a time delay and shifted into a returnedinstruction shift register where it is compared with the instruction sent out (saved in a highway register). If equality is detected, the next instruction is generated, and so on. If no returned instruction is received within the time delay, the next instruction is generated. If an instruction is received within the time delay but is unequal, the next instruction is generated unless the returned instruction is one which only occurs once in the sequence of instructions (as indicated by a content-addressable memory addressed from the returned-instruction shift register). In the latter case, a resynchronization process is entered wherein the control instruction generator is cycled at maximum speed, without application of the instructions to the highway, until an instruction equal to the contents of the returned-instruction shift register is reached, normal operation then resuming if the next instruction from the generator equals the next returned instruction. Thus resynchronization is achieved. If the lastmentioned equality does not hold, the resynchronization process is restarted. Peripheral unit.-Each highway feeds a respective input shift register with the word (instruction) received on it. If all three words are valid (i.e. have the correct number of bits), the word obtained by taking the majority value of corresponding bits is shifted into the third input shift register and also parity checked. If only two of the words are valid, on the other hand, one of them is passed into the third input shift register, and also parity checked. If only one of the words is valid, that word is passed into the third input shift register, and parity checked. A "data good" signal is produced if the parity is correct and at least one of the words is valid and, in the event that precisely two of the words are valid, these two words are equal. The "data good" signal gates the third input shift register to a comparator where the instruction is compared with the instructions to which this peripheral unit should respond from a store (which may include, if desired, the nature of the response). In the event of a match, a data source is gated to an output register which feeds all the channels. Alternatively, data is gated into the peripheral unit from the channels. In either ease, this data operation is preceded by passage of the instruction in the third input shift register via the output register to all the channels.