GB1314021A - Digital data carrying component and associable data transfer device - Google Patents

Abstract

1314021 Portable data carrier; tickets J W HALPERN and W WARD 27 Feb 1970 [28 Feb 1969 11 March 1969 28 March 1969 9 April 1969 5 Sept 1969 22 Dec 1969] 10789/69 53958/72 53959/72 53960/72 44166/69 and 62238/69 Headings G4C G4M and G4T [Also in Divisions H1 and H3] A digital data carrying component and an associable data transfer device has a binary store in the component and a read out coil acting to load pulses produced in the transfer device. In one embodiment power is supplied to an oscillator which produces a predetermined number of pulses when the component in the form of a disc is correctly inserted in the reader (Figs. 1-6, not shown). The pulses are applied to differentiating capacitor C 1 to produce negative pulses in coil L 1 in the component which shift data in register R m . Data "1"s are arranged to render a controlled diode d 4 non- conductive whereas "0"s render the diode conducting and load coil L 1 and coil L 0 so that the positive pulses from the oscillator are reduced in amplitude. The negative pulses are used also to shift register Rd in the sensor and the positive pulses are fed in as data to register R e . In a further embodiment Fig. 9 the sensor is coupled to a computer allowing data read-out to be checked, altered and replaced. The data is read in a similar manner to the above embodiment and data to be rewritten is passed via a gate G 2 , the data having a square wave for a "1" and a sharp leading edge followed by a ramp for a "0" (Fig. 10a, not shown). The component also contains a counter R c , normally holding a "1" in each of its end positions, two delays and an oscillator. Normally gates G 3 and G 1 are enabled and G 2 is inhibited. For read-out counter R c is shifted and after a delay oscillator 2 is enabled to read-out data from register R m until counter R c contains two adjacent "1"s in its leftmost stages. Gate G 3 is closed to prevent recirculation of data, gate G 1 is closed and gate G 4 is closed to prevent further operation of the counter. Data can then be entered via diode D 3 and gate G 2 . After a delay slightly longer than the write period a one shot flip-flop is set which shifts the counter 1 bit and returns it to its normal condition. The storage register may contain transistor bistables having ferrite cores, ferro nickel plating or ferric oxide or ferro-ceramic powder coupled to the collector leads of the transistor to be biased in opposite directions to retain an indication of the state of the data if the voltage supply is removed (Fig. 13, not shown, see Division H3). The component may be in the form of a pen containing cores C, two cores per bit, the data in the cores being shifted by two out of phase clock pulses (Figs. 15, 16, not shown). Data may be held on a magneto-strictive plate or rod (Figs. 18-22, not shown). The component may contain its own battery or may have a coil and a rectifier. The component may be an identity component or a ticket for public transport.