GB1287477A - Improvements in relating to oscillator circuit arrangements - Google Patents
Improvements in relating to oscillator circuit arrangementsInfo
- Publication number
- GB1287477A GB1287477A GB5898069A GB5898069A GB1287477A GB 1287477 A GB1287477 A GB 1287477A GB 5898069 A GB5898069 A GB 5898069A GB 5898069 A GB5898069 A GB 5898069A GB 1287477 A GB1287477 A GB 1287477A
- Authority
- GB
- United Kingdom
- Prior art keywords
- signal
- gate
- capture range
- derived
- controlled oscillator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000010408 sweeping Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
1287477 APC systems LICENTIA PATENT VERWALTUNGS GmbH 3 Dec 1969 [25 Feb 1969] 58980/69 Heading H3A In an APC system, a signal f T derived from the controlled oscillator is fed via two series connected gates Ga 1 , Ga 2 to a phase discriminator (not shown), the derived signal fT being further applied as a timing pulse to a first bi-stable unit BS which has one output terminal Q connected to an arrangement, e.g. multivibrators MF1, MF2, pulse shaper JF1 for producing a signal indicative of the control capture range and another terminal Q for delivering a timing pulse to a second bi-stable unit BS2, the arrangement being such that when the frequency error is within the capture range, BS2 delivers pulses at its Q, Q terminals such that gate Ga1 is held open and a multivibrator AS is switched off so that gate Ga2 is also held open to pass the derived frequency signal and when the error signal is outside the capture range, the pulses at Q, Q are such as to close gate Ga1 and to initiate operation of AS whose output is applied via gate Ga2 to the phase discriminator for sweeping the controlled oscillator until the frequency error fell within the normal capture range, BS1, BS2 may be JK bi-stable flip-flops. Fig. 4 (not shown) indicates the waveforms present at various points of the circuit.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19691909365 DE1909365A1 (en) | 1969-02-25 | 1969-02-25 | Circuit arrangement for synchronizing a free-running oscillator |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1287477A true GB1287477A (en) | 1972-08-31 |
Family
ID=5726249
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB5898069A Expired GB1287477A (en) | 1969-02-25 | 1969-12-03 | Improvements in relating to oscillator circuit arrangements |
Country Status (2)
Country | Link |
---|---|
DE (1) | DE1909365A1 (en) |
GB (1) | GB1287477A (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3818089A1 (en) * | 1988-05-27 | 1989-12-07 | Siemens Ag | Circuit arrangement for the phase synchronisation of clock pulses |
DE3818085A1 (en) * | 1988-05-27 | 1989-12-07 | Siemens Ag | Circuit arrangement for the phase synchronisation of clock pulses |
-
1969
- 1969-02-25 DE DE19691909365 patent/DE1909365A1/en active Pending
- 1969-12-03 GB GB5898069A patent/GB1287477A/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
DE1909365A1 (en) | 1970-08-27 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed | ||
PLNP | Patent lapsed through nonpayment of renewal fees |