GB1277172A - Method of making a large integrated circuit - Google Patents

Method of making a large integrated circuit

Info

Publication number
GB1277172A
GB1277172A GB3246770A GB3246770A GB1277172A GB 1277172 A GB1277172 A GB 1277172A GB 3246770 A GB3246770 A GB 3246770A GB 3246770 A GB3246770 A GB 3246770A GB 1277172 A GB1277172 A GB 1277172A
Authority
GB
United Kingdom
Prior art keywords
units
strips
sub
forming
july
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB3246770A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP5248269A external-priority patent/JPS492871B1/ja
Priority claimed from JP8183169A external-priority patent/JPS493035B1/ja
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of GB1277172A publication Critical patent/GB1277172A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

1277172 Integrated circuits HITACHI Ltd 3 July 1970 [4 July 1969 15 Oct 1969] 32467/70 Heading H1K [Also in Division G4] A method of making a large scale integrated circuit comprises the steps of forming a plurality of spaced apart sub-circuit units in a semiconductor wafer, providing a conductive layer lattice formed around and spaced from each of the said units and etching it to form a plurality of conductive strips, covering these strips with an insulating film, forming openings in this film according to a predetermined pattern to expose the surface of the strips where required, and forming interconnection lines between these strips and the electrodes of the sub-circuit units. The spacings between the spaced apart subcircuit units may be constant, or irregular as when larger spacings are allowed around more complex sub-circuit units. Further to ensure that connections are formed between good units only, the units may be tested before connection, bad units not being used and remaining unconnected. Prior to interconnection, the subcircuit units can be modified if required. An example of the construction of a binary adder by the method is described.
GB3246770A 1969-07-04 1970-07-03 Method of making a large integrated circuit Expired GB1277172A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP5248269A JPS492871B1 (en) 1969-07-04 1969-07-04
JP8183169A JPS493035B1 (en) 1969-10-15 1969-10-15

Publications (1)

Publication Number Publication Date
GB1277172A true GB1277172A (en) 1972-06-07

Family

ID=26393084

Family Applications (1)

Application Number Title Priority Date Filing Date
GB3246770A Expired GB1277172A (en) 1969-07-04 1970-07-03 Method of making a large integrated circuit

Country Status (2)

Country Link
DE (1) DE2033130A1 (en)
GB (1) GB1277172A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2334405A1 (en) * 1972-07-10 1974-01-31 Amdahl Corp LSI LABELS AND METHOD OF MANUFACTURING THE SAME
FR2315804A1 (en) * 1975-06-23 1977-01-21 Ibm HIGH DENSITY ARCHITECTURE FOR SEMICONDUCTOR BLOCK
WO2007086019A1 (en) * 2006-01-26 2007-08-02 Nxp B.V. Production of integrated circuits comprising different components

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2643482A1 (en) * 1976-09-27 1978-03-30 Siemens Ag SEMI-CONDUCTOR PLATE FOR MANUFACTURING HIGHLY INTEGRATED COMPONENTS

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2334405A1 (en) * 1972-07-10 1974-01-31 Amdahl Corp LSI LABELS AND METHOD OF MANUFACTURING THE SAME
FR2315804A1 (en) * 1975-06-23 1977-01-21 Ibm HIGH DENSITY ARCHITECTURE FOR SEMICONDUCTOR BLOCK
WO2007086019A1 (en) * 2006-01-26 2007-08-02 Nxp B.V. Production of integrated circuits comprising different components

Also Published As

Publication number Publication date
DE2033130A1 (en) 1971-02-04

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Legal Events

Date Code Title Description
PS Patent sealed
PLNP Patent lapsed through nonpayment of renewal fees