GB1268627A - Improvements in or relating to digital modulation systems - Google Patents

Abstract

1,268,627. Digital transmission systems. PLESSEY TELECOMMUNICATIONS RESEARCH Ltd. 14 July, 1969 [12 July, 1968], No. 33466/68. Heading H4P. Binary data M to be transmitted in differential phase duobinary form is applied to modulo- 2 adder 2 whose other input B is the 2-bit delayed output C of the adder. The adder output C is also fed via a filter 7, having a response defined in the Specification and giving a duobinary output, to a mixer 9 and is also fed to a second modulo-2 adder 6 whose other input is a half bit-rate square-wave clock signal D. The output of adder 6 is fed to a second mixer 10 via a second filter 8. The mixers are fed by carriers 90 degrees apart and the sum S of their outputs is the signal applied to the transmission channel. Various demodulators are described as indicated below. Fig. 5: the received signal 5 is mixed at 16 with a carrier from oscillator 17. After band pass filtering the mixer output passes to mixers 19, 22. It is also fed through a 1-bit delay direct and with 90 degrees displacement to the mixers which feed low pass filters 21, 24. The modulus of the output J of filter 24 is subtracted from the output I of filter 21, the resulting signal K being gated by bit-rate clock pulses A. The gate's output controls a bi-stable 28 to develop a binary output M identical to the input of the transmitter. The clock pulses A are derived from signal K by the units 29-33 shown. Oscillator 17 is synchronized by the filtered signal J. Fig. 7 (not shown): the received signal is fed to two channels each consisting of a mixer (36, 37) fed by carriers 90 degrees apart and feeding a low pass filter (40, 41). Each filter feeds direct and via a 1-bit delay (42, 43) an arrangement of four mixers feeding adding and subtracting units (46, 49) which give respective outputs I, J. The remainder of the circuit is identical to that shown in Fig. 5 consisting of units 25-28. Fig. 8: the received signal passes to mixers fed by carriers 90 degrees apart. After filtering the mixers' outputs P(t), Q(t) are fed to a first circuit comprising differentiators 52, 53, mixers 54, 55 and subtractor 56 to develop a signal R. The outputs are also fed to a second circuit comprising squaring units 58, 59 and adder 60. The difference U of the output of the adder and the modulus of R is formed at 61 and sampled at 62 with clock pulses V. The samples control bi-stable 63 which delivers the binary output M. Fig. 10 (not shown): the received signal passes to mixers fed with 90-degree carriers as before, the filtered outputs (W, X) passing to gates where they are sampled by 90-degree displaced half bit-rate clock pulses from an oscillator controlled by the difference of the moduli of the outputs W, X. The samples control a monostable which delivers a binary signal direct and via 2-bit delay to a modulo-2 adder whose output is the demodulated binary signal. The carriers are generated by a phase-lock loop fed by outputs W and X and including, subtracters, gates, and adders.