GB1243800A - Synchronous binary-decimal reversible counter - Google Patents
Synchronous binary-decimal reversible counterInfo
- Publication number
- GB1243800A GB1243800A GB4451268A GB4451268A GB1243800A GB 1243800 A GB1243800 A GB 1243800A GB 4451268 A GB4451268 A GB 4451268A GB 4451268 A GB4451268 A GB 4451268A GB 1243800 A GB1243800 A GB 1243800A
- Authority
- GB
- United Kingdom
- Prior art keywords
- decimal
- skips
- sept
- read
- reversible counter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K21/00—Details of pulse counters or frequency dividers
Landscapes
- Measurement Of Unknown Time Intervals (AREA)
- Manipulation Of Pulses (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
1,243,800. Reversible counters. PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd. 19 Sept., 1968 [22 Sept., 1967], No. 44512/68. Heading G4A. A four-stage reversible decimal counter uses different code combinations for representation of some of the decimal digits according to whether the counter is operating in forward or reverse. In one embodiment (Fig. 3, not shown), the system operates in binary notation, Fig. 1, column H, up to 9 in forward operation, at which point conventional feedback over leads (h 1 , h 2 , not shown) restore all stages with carry in response to the next pulse. In reverse counting the step from 8 to 7 skips codes 13-8 by feedback leads (t 1 , t 2 , not shown). Read-out is effected by AND gates fed by the stages indicated by underlining, read-out for digits 8, 9 being thus unambiguous. In a modification a 2, 4, 4, 1 code is used, Fig. 2, with the skips shown.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| NL6712934A NL6712934A (en) | 1967-09-22 | 1967-09-22 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB1243800A true GB1243800A (en) | 1971-08-25 |
Family
ID=19801267
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB4451268A Expired GB1243800A (en) | 1967-09-22 | 1968-09-19 | Synchronous binary-decimal reversible counter |
Country Status (3)
| Country | Link |
|---|---|
| FR (1) | FR1582709A (en) |
| GB (1) | GB1243800A (en) |
| NL (1) | NL6712934A (en) |
-
1967
- 1967-09-22 NL NL6712934A patent/NL6712934A/xx unknown
-
1968
- 1968-09-19 GB GB4451268A patent/GB1243800A/en not_active Expired
- 1968-09-20 FR FR1582709D patent/FR1582709A/fr not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| DE1762840A1 (en) | 1970-09-17 |
| NL6712934A (en) | 1969-03-25 |
| FR1582709A (en) | 1969-10-03 |
| DE1762840B2 (en) | 1976-10-21 |
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