GB1208578A - Methods of manufacturing semiconductor devices - Google Patents

Methods of manufacturing semiconductor devices

Info

Publication number
GB1208578A
GB1208578A GB2751770A GB2751770A GB1208578A GB 1208578 A GB1208578 A GB 1208578A GB 2751770 A GB2751770 A GB 2751770A GB 2751770 A GB2751770 A GB 2751770A GB 1208578 A GB1208578 A GB 1208578A
Authority
GB
United Kingdom
Prior art keywords
silicon
layer
masking
oxide
oct
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB2751770A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Philips Electronics UK Ltd
Original Assignee
Philips Electronic and Associated Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from NL666614016A external-priority patent/NL153374B/en
Application filed by Philips Electronic and Associated Industries Ltd filed Critical Philips Electronic and Associated Industries Ltd
Publication of GB1208578A publication Critical patent/GB1208578A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0635—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors and diodes, or resistors, or capacitors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Formation Of Insulating Films (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)

Abstract

1,208,578. Semi-conductor devices. PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd. 2 Oct., 1967 [5 Oct., 1966], No. 27517/70. Divided out of 1,208,574. Heading H1K. A method of manufacturing a semi-conductor device having a substantially flat silicon oxide surface layer comprises subjecting a semiconductor silicon body to an oxidizing treatment whilst a selected portion of its surface is masked against oxidation by means of a masking layer and causing an oxide of silicon to grow into the silicon at the unmasked portions until the grown oxide forms a layer which is sunk over at least part of its thickness in the body. The surface masking during the formation of the silicon oxide layer is provided by a layer of silicon nitride, and this mask is further used, after its removal over selected areas, for masking the exposed silicon surface during diffusion of impurities into that surface to form PN junctions in the body. For the production of a transistor, a second surface oxidizing treatment is performed to convert this selected surface portion, into which impurity has been diffused, into a second silicon oxide layer thinner than the previously grown oxide layer. The remainder of the surface mask is then removed and a further impurity diffused into the silicon surface. Specifications 1,208,574, 1,208,575, 1,208,576 and 1,208,577 are referred to.
GB2751770A 1966-10-05 1967-10-02 Methods of manufacturing semiconductor devices Expired GB1208578A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
NL666614016A NL153374B (en) 1966-10-05 1966-10-05 PROCESS FOR THE MANUFACTURE OF A SEMICONDUCTOR DEVICE PROVIDED WITH AN OXIDE LAYER AND SEMI-CONDUCTOR DEVICE MANUFACTURED ACCORDING TO THE PROCEDURE.
GB44763/67A GB1208574A (en) 1966-10-05 1967-10-02 Methods of manufacturing semiconductor devices

Publications (1)

Publication Number Publication Date
GB1208578A true GB1208578A (en) 1970-10-14

Family

ID=26265451

Family Applications (4)

Application Number Title Priority Date Filing Date
GB2751670A Expired GB1208577A (en) 1966-10-05 1967-10-02 Methods of manufacturing semiconductor devices
GB2751770A Expired GB1208578A (en) 1966-10-05 1967-10-02 Methods of manufacturing semiconductor devices
GB2723970A Expired GB1208576A (en) 1966-10-05 1967-10-02 Methods of manufacturing semiconductor devices
GB2723870A Expired GB1208575A (en) 1966-10-05 1967-10-02 Methods of manufacturing semiconductor devices

Family Applications Before (1)

Application Number Title Priority Date Filing Date
GB2751670A Expired GB1208577A (en) 1966-10-05 1967-10-02 Methods of manufacturing semiconductor devices

Family Applications After (2)

Application Number Title Priority Date Filing Date
GB2723970A Expired GB1208576A (en) 1966-10-05 1967-10-02 Methods of manufacturing semiconductor devices
GB2723870A Expired GB1208575A (en) 1966-10-05 1967-10-02 Methods of manufacturing semiconductor devices

Country Status (1)

Country Link
GB (4) GB1208577A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2441170A1 (en) * 1973-09-07 1975-03-13 Philips Nv METHOD OF MANUFACTURING A SEMICONDUCTOR ARRANGEMENT
US4592128A (en) * 1984-06-04 1986-06-03 Inmos Corporation Method for fabricating integrated circuits with polysilicon resistors
US4596071A (en) * 1983-09-05 1986-06-24 Oki Electric Industry Co., Ltd. Method of making semiconductor devices having dielectric isolation regions

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3648125A (en) * 1971-02-02 1972-03-07 Fairchild Camera Instr Co Method of fabricating integrated circuits with oxidized isolation and the resulting structure

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2441170A1 (en) * 1973-09-07 1975-03-13 Philips Nv METHOD OF MANUFACTURING A SEMICONDUCTOR ARRANGEMENT
US4596071A (en) * 1983-09-05 1986-06-24 Oki Electric Industry Co., Ltd. Method of making semiconductor devices having dielectric isolation regions
US4592128A (en) * 1984-06-04 1986-06-03 Inmos Corporation Method for fabricating integrated circuits with polysilicon resistors

Also Published As

Publication number Publication date
GB1208576A (en) 1970-10-14
GB1208575A (en) 1970-10-14
GB1208577A (en) 1970-10-14

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Legal Events

Date Code Title Description
PS Patent sealed
PE20 Patent expired after termination of 20 years