GB1195262A - Conversion and Calculating Arrangements Employing Logarithmitic and/or Exponential Relationships between Input and Output Quantities - Google Patents
Conversion and Calculating Arrangements Employing Logarithmitic and/or Exponential Relationships between Input and Output QuantitiesInfo
- Publication number
- GB1195262A GB1195262A GB28356/67A GB2835667A GB1195262A GB 1195262 A GB1195262 A GB 1195262A GB 28356/67 A GB28356/67 A GB 28356/67A GB 2835667 A GB2835667 A GB 2835667A GB 1195262 A GB1195262 A GB 1195262A
- Authority
- GB
- United Kingdom
- Prior art keywords
- counter
- digital
- pulses
- count
- exponential
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
-
- G—PHYSICS
- G04—HOROLOGY
- G04F—TIME-INTERVAL MEASURING
- G04F10/00—Apparatus for measuring unknown time intervals by electric means
- G04F10/04—Apparatus for measuring unknown time intervals by electric means by counting pulses or half-cycles of an ac
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06J—HYBRID COMPUTING ARRANGEMENTS
- G06J1/00—Hybrid computing arrangements
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/50—Analogue/digital converters with intermediate conversion to time interval
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Mathematical Physics (AREA)
- Automation & Control Theory (AREA)
- Evolutionary Computation (AREA)
- Fuzzy Systems (AREA)
- Software Systems (AREA)
- Power Engineering (AREA)
- Control Of Amplification And Gain Control (AREA)
Abstract
1,195,262. Logarithmic/exponential analoguedigital and digital-digital converter; calculating apparatus. INTELLIGENT INSTRUMENTS Inc. 20 June, 1967, No. 28356/67. Headings G4A and G4H. Analogue-digital and digital-digital converter.-By controlling the frequency of a unijunction transistor relaxation oscillator 99, Fig. 4, (circuit-Fig. 1, not shown) to be proportional to the count in a multi-cathode type counter 100 (Fig. 3, not shown), which also counts the pulses from the oscillator, the count( and the oscillator frequency) will rise exponentially with time, and thus if counting is allowed to continue for a period proportional to x, either by direct control of the oscillator or by a gate between the oscillator and the counter, then the final count will be proportional to e<SP>x</SP>. Frequency control of the oscillator is effected by a feedback form appropriately weighted cathode resistors in the counter. Digital-to-analogue and digital-to-digital conversion is effected by allowing counting 100, Fig. 5, to continue until the count 109 is equal to the digital input 111, and by using the coincidence signal 112 either to gate out the level reached by a linear sawtooth generator 114, or to stop constant frequency clock-pulses 119 passing to a second counter 121, respectively. In both cases the conversion is logarithmic. Exponential digital-to-digital conversion can be effected by inserting a number in counter 121 and by allowing counting to continue in counter 10 (starting from zero) until counter 121 has been stepped backwards to zero by the constant frequency clock-pulses. Calculating apparatus.-The above logarithmic and exponential digital-digital conversions can be used to effect multiplication of division. Thus, for multiplication for example, counting 121 of clock pulses 119, Fig. 6, continues until the count 100 of exponential pulses 99 equals the multiplier 111; then counter 100 is zeroized and counting 121 of clock pulses 99 continues until the count 100 of exponential pulses 99 equals the multiplicand; and finally counter 100 is again zeroized and counting of exponential pulses 99 recommenced until the counter 121 has been stepped backwards to zero by the clock pulses 119. The product then stands in counter 100. Division is similar, the only difference being that counter 121 must count backwards when the divisor is being entered. The quotient, like the product, appears in counter 100.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB28356/67A GB1195262A (en) | 1967-06-20 | 1967-06-20 | Conversion and Calculating Arrangements Employing Logarithmitic and/or Exponential Relationships between Input and Output Quantities |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB28356/67A GB1195262A (en) | 1967-06-20 | 1967-06-20 | Conversion and Calculating Arrangements Employing Logarithmitic and/or Exponential Relationships between Input and Output Quantities |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1195262A true GB1195262A (en) | 1970-06-17 |
Family
ID=10274370
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB28356/67A Expired GB1195262A (en) | 1967-06-20 | 1967-06-20 | Conversion and Calculating Arrangements Employing Logarithmitic and/or Exponential Relationships between Input and Output Quantities |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB1195262A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1999021063A1 (en) * | 1997-10-16 | 1999-04-29 | The Victoria University Of Manchester | Timing circuit |
-
1967
- 1967-06-20 GB GB28356/67A patent/GB1195262A/en not_active Expired
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1999021063A1 (en) * | 1997-10-16 | 1999-04-29 | The Victoria University Of Manchester | Timing circuit |
US6434211B1 (en) | 1997-10-16 | 2002-08-13 | The Victoria University Of Manchester | Timing circuit |
AU757820B2 (en) * | 1997-10-16 | 2003-03-06 | University Of Manchester, The | Timing circuit |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed | ||
PLNP | Patent lapsed through nonpayment of renewal fees |