GB1114798A - Integrated circuit device with dielectric isolation and method of making the same - Google Patents

Abstract

1,114,798. Semi-conductor devices. WESTINGHOUSE ELECTRIC CORPORATION. 15 July, 1966 [9 Aug., 1965; 20 Aug., 1965 (2)], No. 31804/66. Heading H1K. Semi-conductor bodies 10a, b, c which comprise the elements of an integrated circuit device, are supported by a substrate 14 and are insulated from one another and from the substrate 14 at least partially by a layer 12 of material harder than that of the bodies 10a, b, c. The layer 12 may be, for example, of silicon carbide, the semi-conductor bodies being of silicon. The layer 12 is formed by deposition on a semi-conductor block (10), Fig. 2 (not shown) having grooves (11), formed by mechanical scribing or etching and corresponding in shape to the desired configuration of the layer 12, Fig. 5. The deposition of the layer 12 of silicon carbide is preferably by pyrolytic decomposition of methylsilanes or halogenated methylsilanes in an inert atmosphere, or alternatively SiCl 4 and propane may be caused to react together in hydrogen. The substrate 14 is then formed, e.g. by epitaxial deposition over the layer 12. The side of the resulting wafer remote from the substrate 14 is then ground or etched down to the level of the portions of the layer 14 in the bases of the grooves (11), so producing isolated semi-conductor bodies 10a, b, c. The relative hardness of the layer 12 provides a means of indicating when the grinding or etching process has reached the desired stage. The required P or N regions are diffused into the bodies 10a, b, c, which are then coated with an insulating layer 30 of, e.g. silicon dioxide, and the necessary ohmic contacts 24 are made through the layer 30. In order to improve the insulating properties of the layer 12, it may be composite, comprising a layer of silicon dioxide as well as the relatively hard layer of e.g. silicon carbide. In a second embodiment a composite layer is applied to an N-type semi-conductor body (50), Fig. 6 (not shown), having two sets of grooves (56, 58) of differing depth. An N+ layer (55), may be formed by epitaxy or diffusion on the body (50) prior to grooving. This may be replaced by a layer of Ta, Ti or Mo. After deposition of the substrate (64), Fig. 7 (not shown), the body (50) is ground or etched to the level of the relatively hard layer (60) at the bases of the deeper set of grooves (56). Subsequent controlled removal of more material to the required level is then relatively easy. Further embodiments are described, Figs 10, 11 (not shown), in which the semiconductor starting material, on which the relatively hard insulating layer is deposited, is first coated with alternate layers of insulator and semi-conductor. In these embodiments individual semi-conductor elements of the integrated circuit device are insulated from each other by silicon dioxide, groups of elements being insulated by relatively hard layers of silicon carbide. The groups may be separated into individual circuits.