GB1016429A - Data processing system - Google Patents

Abstract

1,016,429. Electric digital data-storage. INTERNATIONAL BUSINESS MACHINES CORPORATION. Dec. 2, 1963 [Dec. 31, 1962], No. 47402/63. Heading G4C. Selected ones of m x n words in a memory are read out by interrogating an m x n element detector plane to set an m-stage and an n-stage register, the stages of which control corresponding stages of skipping registers which are interrogated to provide signals to the columns and rows of the memory respectively. The detector plane and memory are core matrices and the former has previously been set as a result of an associative interrogation of the memory. All columns in the detector plane are read-out to set selections of m " detector plane " flip-flops and n " detector plane " flip-flops, a given one of the former flip-flops being set if the column to which it corresponds contains a set core, and the latter flip-flops relating to the rows in a similar manner. Those of the m and n flip-flops which are set prime corresponding flip-flops in m and n-stage skipping registers respectively. The first primed flip-flop in m skipping register is set and the n " detector plane " flip-flops are reset. The set flip-flop in the m skipping register applies a signal to read-out the corresponding column of the detector plane into the n " detector plane " flip-flops. The first primed flip-flop in the n skipping register is set. This then supplies a signal to the memory where the coincidence of this signal and one from the set flip-flop in the m skipping register results in read-out of a word from the memory. This read-out results in a signal which resets the set flip-flop in the n skipping register and sets the next primed flip-flop therein. The next required word in the same column of the memory is thereupon read-out with advance of the n skipping register. This continues until the last primed flip-flop in the n skipping register has been set (and reset) when a signal produced from the n skipping register resets the n " detector plane " flip-flops and advances the m skipping register to the next primed flip-flop whereupon the corresponding column of the detector plane is read-out into the n " detector plane " flipflops, and so on. When the last primed flipflop of the m skipping register has been set (and reset) a completion indicator is actuated. By changing various switches over, fencing-off means may be connected into the circuit. By setting appropriate cores of a fence plane identical to the detector plane, read-out of words in any desired column or row of the memory may be prevented even though the corresponding cores in the detector plane are set. Read-out of any column of the detector plane into the m and n " detector plane " flipflops is now accompanied by read-out of the corresponding column of the fence plane into m and n " fence plane " flip-flops. The latter are reset whenever the m and n " detector plane " are reset respectively. Control of the skipping registers from " detector plane " flipflops is now via sets of (AND and OR) gates controlled by the " fence plane " flip-flops so that a given (set) " detector plane " flip-flop can prime the corresponding skipping register flip-flop if and only if the corresponding " fence plane " flip-flop is set. Figs. 3A-3B (not shown) show a modification in which two fence planes (with associated flip-flops) are provided and priming takes place only if the flip-flops of both fence planes (corresponding to the set " detector plane " flip-flop) are set. Manual change-over switches may be provided to allow operation using one fence plane only, if desired. Fig. 4 (not shown) shows a further modification in which a set flip-flop associated with either or both of the fence planes will allow priming. Fig. 5 (not shown) shows a modification in which priming takes place if and only if the set detector plane flip-flop corresponds to a set flip-flop relating to one fence plane and an unset flip-flop relating to the other fence plane. The cores of the detector and fence planes are adapted for non-destructive read-out by using short-duration read-out pulses, multiaperture devices, or two-core-per-bit devices where the cores are destructively read-out but only one at a time.