GB0807148D0 - Clock distribution buffer - Google Patents

Clock distribution buffer

Info

Publication number
GB0807148D0
GB0807148D0 GB0807148A GB0807148A GB0807148D0 GB 0807148 D0 GB0807148 D0 GB 0807148D0 GB 0807148 A GB0807148 A GB 0807148A GB 0807148 A GB0807148 A GB 0807148A GB 0807148 D0 GB0807148 D0 GB 0807148D0
Authority
GB
United Kingdom
Prior art keywords
clock distribution
distribution buffer
buffer
clock
distribution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
GB0807148A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Elonics Ltd
Original Assignee
Elonics Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Elonics Ltd filed Critical Elonics Ltd
Priority to GB0807148A priority Critical patent/GB0807148D0/en
Publication of GB0807148D0 publication Critical patent/GB0807148D0/en
Priority to PCT/GB2009/050279 priority patent/WO2009127848A2/en
Priority to EP09732693A priority patent/EP2277267A2/en
Ceased legal-status Critical Current

Links

GB0807148A 2008-04-18 2008-04-18 Clock distribution buffer Ceased GB0807148D0 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
GB0807148A GB0807148D0 (en) 2008-04-18 2008-04-18 Clock distribution buffer
PCT/GB2009/050279 WO2009127848A2 (en) 2008-04-18 2009-03-25 Clock distribution buffer
EP09732693A EP2277267A2 (en) 2008-04-18 2009-03-25 Clock distribution buffer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB0807148A GB0807148D0 (en) 2008-04-18 2008-04-18 Clock distribution buffer

Publications (1)

Publication Number Publication Date
GB0807148D0 true GB0807148D0 (en) 2008-05-21

Family

ID=39472384

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0807148A Ceased GB0807148D0 (en) 2008-04-18 2008-04-18 Clock distribution buffer

Country Status (3)

Country Link
EP (1) EP2277267A2 (en)
GB (1) GB0807148D0 (en)
WO (1) WO2009127848A2 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110292855A1 (en) * 2010-05-28 2011-12-01 Qualcomm Incorporated Dynamic clock buffer power optimization based on modes of operation
US9054682B2 (en) 2013-02-05 2015-06-09 International Business Machines Corporation Wide bandwidth resonant global clock distribution
US9058130B2 (en) 2013-02-05 2015-06-16 International Business Machines Corporation Tunable sector buffer for wide bandwidth resonant global clock distribution
US8704576B1 (en) 2013-02-05 2014-04-22 International Business Machines Corporation Variable resistance switch for wide bandwidth resonant global clock distribution
CN103399808B (en) * 2013-06-06 2016-05-04 北京航天自动控制研究所 A kind of method that realizes the two redundancies of crystal oscillator in flight control computer
US9847776B2 (en) * 2014-07-14 2017-12-19 Finisar Corporation Multi-rate clock buffer
KR102641515B1 (en) * 2016-09-19 2024-02-28 삼성전자주식회사 Memory device and clock distribution method thereof
CN108089487B (en) * 2017-11-03 2020-07-24 成都赛英科技有限公司 Adjustable video pulse signal source

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6147543A (en) * 1996-01-19 2000-11-14 Motorola, Inc. Method and apparatus for selecting from multiple mixers
US6218858B1 (en) * 1999-01-27 2001-04-17 Xilinx, Inc. Programmable input/output circuit for FPGA for use in TTL, GTL, GTLP, LVPECL and LVDS circuits
US6683472B2 (en) * 2002-02-19 2004-01-27 Rambus Inc. Method and apparatus for selectably providing single-ended and differential signaling with controllable impedance and transition time
US6922091B2 (en) * 2002-09-03 2005-07-26 Rambus Inc. Locked loop circuit with clock hold function
US7061273B2 (en) * 2003-06-06 2006-06-13 Rambus Inc. Method and apparatus for multi-mode driver
US7446576B2 (en) * 2005-09-30 2008-11-04 Slt Logics, Llc Output driver with slew rate control
FR2900003A1 (en) * 2006-04-13 2007-10-19 St Microelectronics Sa BUFFER CIRCUIT COMPRISING MEANS FOR CONTROLLING THE SLOPE OF THE OUTPUT SIGNAL

Also Published As

Publication number Publication date
WO2009127848A3 (en) 2009-12-23
EP2277267A2 (en) 2011-01-26
WO2009127848A2 (en) 2009-10-22

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Legal Events

Date Code Title Description
AT Applications terminated before publication under section 16(1)