GB0216753D0 - Method and structure for DC and RF shielding of integrated circuits - Google Patents

Method and structure for DC and RF shielding of integrated circuits

Info

Publication number
GB0216753D0
GB0216753D0 GBGB0216753.4A GB0216753A GB0216753D0 GB 0216753 D0 GB0216753 D0 GB 0216753D0 GB 0216753 A GB0216753 A GB 0216753A GB 0216753 D0 GB0216753 D0 GB 0216753D0
Authority
GB
United Kingdom
Prior art keywords
shielding
integrated circuits
circuits
integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GBGB0216753.4A
Other versions
GB2382222A (en
GB2382222B (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Agere Systems LLC
Original Assignee
Agere Systems Guardian Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agere Systems Guardian Corp filed Critical Agere Systems Guardian Corp
Publication of GB0216753D0 publication Critical patent/GB0216753D0/en
Publication of GB2382222A publication Critical patent/GB2382222A/en
Application granted granted Critical
Publication of GB2382222B publication Critical patent/GB2382222B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528Geometry or layout of the interconnection structure
    • H01L23/5283Cross-sectional geometry
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/552Protection against radiation, e.g. light or electromagnetic waves
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64Impedance arrangements
    • H01L23/66High-frequency adaptations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64Impedance arrangements
    • H01L2223/66High-frequency adaptations
    • H01L2223/6605High-frequency electrical connections
    • H01L2223/6616Vertical connections, e.g. vias
    • H01L2223/6622Coaxial feed-throughs in active or passive substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
GB0216753A 2001-07-23 2002-07-18 Method and structure for DC and RF shielding of integrated circuits Expired - Fee Related GB2382222B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/911,364 US6844236B2 (en) 2001-07-23 2001-07-23 Method and structure for DC and RF shielding of integrated circuits

Publications (3)

Publication Number Publication Date
GB0216753D0 true GB0216753D0 (en) 2002-08-28
GB2382222A GB2382222A (en) 2003-05-21
GB2382222B GB2382222B (en) 2005-10-05

Family

ID=25430129

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0216753A Expired - Fee Related GB2382222B (en) 2001-07-23 2002-07-18 Method and structure for DC and RF shielding of integrated circuits

Country Status (5)

Country Link
US (1) US6844236B2 (en)
JP (2) JP4834862B2 (en)
KR (1) KR100892226B1 (en)
GB (1) GB2382222B (en)
TW (1) TW550777B (en)

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US6765296B2 (en) * 2002-01-10 2004-07-20 Chartered Semiconductor Manufacturing Ltd. Via-sea layout integrated circuits
US7741696B2 (en) * 2004-05-13 2010-06-22 St-Ericsson Sa Semiconductor integrated circuit including metal mesh structure
US7411279B2 (en) * 2004-06-30 2008-08-12 Endwave Corporation Component interconnect with substrate shielding
US7348666B2 (en) * 2004-06-30 2008-03-25 Endwave Corporation Chip-to-chip trench circuit structure
US7071530B1 (en) * 2005-01-27 2006-07-04 International Business Machines Corporation Multiple layer structure for substrate noise isolation
DE102005046624B3 (en) * 2005-09-29 2007-03-22 Atmel Germany Gmbh Production of semiconductor arrangement with formation of conductive substrate, structural element region (SER) layer for insulating SER from substrate useful in semiconductor technology, e.g. in production of DMOS-field effect transistors
US20080001262A1 (en) * 2006-06-29 2008-01-03 Telesphor Kamgaing Silicon level solution for mitigation of substrate noise
US7687311B1 (en) * 2008-11-13 2010-03-30 Taiwan Semiconductor Manufacturing Company, Ltd. Method for producing stackable dies
US9520547B2 (en) 2013-03-15 2016-12-13 International Business Machines Corporation Chip mode isolation and cross-talk reduction through buried metal layers and through-vias
US9219298B2 (en) 2013-03-15 2015-12-22 International Business Machines Corporation Removal of spurious microwave modes via flip-chip crossover
US10141271B1 (en) 2017-03-17 2018-11-27 CoolStar Technology, Inc. Semiconductor device having enhanced high-frequency capability and methods for making same

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JPS61166539U (en) * 1985-04-05 1986-10-16
JPH0783050B2 (en) * 1985-06-21 1995-09-06 株式会社東芝 Method for manufacturing semiconductor device
FR2605828A1 (en) * 1986-10-28 1988-04-29 Univ Metz THERMAL OR MECHANICAL COMPRESSOR COMPENSATION ELEMENT, IN PARTICULAR FOR A PRINTED CIRCUIT, AND METHOD FOR MANUFACTURING SUCH A COMPONENT IMPLEMENTED IN A PRINTED CIRCUIT
JPS6444039A (en) * 1987-08-12 1989-02-16 Hitachi Ltd Dielectric isolation substrate
DE340959T1 (en) 1988-05-06 1990-08-16 Digital Equipment Corp., Maynard, Mass., Us CIRCUIT CHIP PACK FOR PROTECTION AGAINST ELECTROMAGNETIC INTERFERENCES, ELECTROSTATIC DISCHARGES AND THERMAL AND MECHANICAL VOLTAGES.
JP2767843B2 (en) * 1988-12-15 1998-06-18 日本電気株式会社 Analog / digital mixed circuit
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US5306942A (en) * 1989-10-11 1994-04-26 Nippondenso Co., Ltd. Semiconductor device having a shield which is maintained at a reference potential
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US5761053A (en) * 1996-05-08 1998-06-02 W. L. Gore & Associates, Inc. Faraday cage
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Also Published As

Publication number Publication date
JP2003152093A (en) 2003-05-23
KR100892226B1 (en) 2009-04-09
GB2382222A (en) 2003-05-21
KR20030011583A (en) 2003-02-11
JP2011176339A (en) 2011-09-08
US6844236B2 (en) 2005-01-18
JP4834862B2 (en) 2011-12-14
US20030015772A1 (en) 2003-01-23
GB2382222B (en) 2005-10-05
TW550777B (en) 2003-09-01

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20160718