FR3130412B1 - Dispositif mémoire DRAM mettant un œuvre un mécanisme de gestion du martelage de rang - Google Patents
Dispositif mémoire DRAM mettant un œuvre un mécanisme de gestion du martelage de rang Download PDFInfo
- Publication number
- FR3130412B1 FR3130412B1 FR2113218A FR2113218A FR3130412B1 FR 3130412 B1 FR3130412 B1 FR 3130412B1 FR 2113218 A FR2113218 A FR 2113218A FR 2113218 A FR2113218 A FR 2113218A FR 3130412 B1 FR3130412 B1 FR 3130412B1
- Authority
- FR
- France
- Prior art keywords
- hammering
- rank
- ranks
- memory device
- increment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000000694 effects Effects 0.000 abstract 2
- 230000006870 function Effects 0.000 abstract 2
- 230000003247 decreasing effect Effects 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40603—Arbitration, priority and concurrent access to memory cells for read/write or refresh operations
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Dram (AREA)
- Read Only Memory (AREA)
Abstract
L’invention concerne un Dispositif mémoire qui comprend : - un tableau de mémoire pourvu de n rangs de mémoire, chaque rang i étant susceptible d’exercer un martelage de rang de portée p; - un bloc de prévention de l’effet de martelage qui comprend des moyens de comptage mettant en œuvre m compteurs de martelage, chaque compteur k étant associé à un ou plusieurs des rangs i, et est configuré pour incrémenter un comptage k d’une valeur d’incrément kN, la valeur d’incrément kN étant une fonction décroissante de la durée TPN et également fonction de la durée TAN, la valeur d’incrément kN quantifiant l’effet de martelage de l’un ou plusieurs des rangs i sur des rangs j à portée de martelage ; - un bloc de rafraîchissement de rang configuré pour rafraîchir un ou plusieurs rangs dès lors qu’un comptage k atteint une valeur seuil M. Figure 1
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR2113218A FR3130412B1 (fr) | 2021-12-09 | 2021-12-09 | Dispositif mémoire DRAM mettant un œuvre un mécanisme de gestion du martelage de rang |
PCT/EP2022/084811 WO2023104891A1 (fr) | 2021-12-09 | 2022-12-07 | Dispositif mémoire dram mettant en œuvre un mécanisme de gestion du martelage de rang |
CN202280079179.7A CN118339612A (zh) | 2021-12-09 | 2022-12-07 | 使用用于行锤击管理的机制的dram存储器设备 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR2113218 | 2021-12-09 | ||
FR2113218A FR3130412B1 (fr) | 2021-12-09 | 2021-12-09 | Dispositif mémoire DRAM mettant un œuvre un mécanisme de gestion du martelage de rang |
Publications (2)
Publication Number | Publication Date |
---|---|
FR3130412A1 FR3130412A1 (fr) | 2023-06-16 |
FR3130412B1 true FR3130412B1 (fr) | 2023-12-22 |
Family
ID=80786491
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR2113218A Active FR3130412B1 (fr) | 2021-12-09 | 2021-12-09 | Dispositif mémoire DRAM mettant un œuvre un mécanisme de gestion du martelage de rang |
Country Status (3)
Country | Link |
---|---|
CN (1) | CN118339612A (fr) |
FR (1) | FR3130412B1 (fr) |
WO (1) | WO2023104891A1 (fr) |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR3066842B1 (fr) | 2017-05-24 | 2019-11-08 | Upmem | Logique de correction de row hammer pour dram avec processeur integre |
US11158364B2 (en) * | 2019-05-31 | 2021-10-26 | Micron Technology, Inc. | Apparatuses and methods for tracking victim rows |
FR3111731B1 (fr) | 2020-06-23 | 2023-01-06 | Upmem | Procédé et circuit de protection d’un dispositif de mémoire DRAM de l’effet de martelagede rang |
CN112786087B (zh) * | 2021-03-15 | 2022-04-26 | 长鑫存储技术有限公司 | 刷新电路及存储器 |
-
2021
- 2021-12-09 FR FR2113218A patent/FR3130412B1/fr active Active
-
2022
- 2022-12-07 WO PCT/EP2022/084811 patent/WO2023104891A1/fr unknown
- 2022-12-07 CN CN202280079179.7A patent/CN118339612A/zh active Pending
Also Published As
Publication number | Publication date |
---|---|
CN118339612A (zh) | 2024-07-12 |
FR3130412A1 (fr) | 2023-06-16 |
WO2023104891A1 (fr) | 2023-06-15 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PLFP | Fee payment |
Year of fee payment: 2 |
|
PLSC | Publication of the preliminary search report |
Effective date: 20230616 |
|
PLFP | Fee payment |
Year of fee payment: 3 |