FR3121249B1 - Procédé d’implémentation d’un module logiciel défini par un graphe orienté non cyclique non imbriqué en environnement multi-cœur - Google Patents

Procédé d’implémentation d’un module logiciel défini par un graphe orienté non cyclique non imbriqué en environnement multi-cœur Download PDF

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Publication number
FR3121249B1
FR3121249B1 FR2103153A FR2103153A FR3121249B1 FR 3121249 B1 FR3121249 B1 FR 3121249B1 FR 2103153 A FR2103153 A FR 2103153A FR 2103153 A FR2103153 A FR 2103153A FR 3121249 B1 FR3121249 B1 FR 3121249B1
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France
Prior art keywords
implementing
software module
nested
module defined
directed graph
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FR2103153A
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English (en)
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FR3121249A1 (fr
Inventor
Nicolas Romea
Julien Durand
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Vitesco Technologies
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Vitesco Technologies
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Publication date
Application filed by Vitesco Technologies filed Critical Vitesco Technologies
Priority to FR2103153A priority Critical patent/FR3121249B1/fr
Priority to CN202280025557.3A priority patent/CN117099080A/zh
Priority to US18/276,947 priority patent/US20240118879A1/en
Priority to PCT/EP2022/057593 priority patent/WO2022207424A1/fr
Publication of FR3121249A1 publication Critical patent/FR3121249A1/fr
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Publication of FR3121249B1 publication Critical patent/FR3121249B1/fr
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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/45—Exploiting coarse grain parallelism in compilation, i.e. parallelism between groups of instructions
    • G06F8/451—Code distribution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/45—Exploiting coarse grain parallelism in compilation, i.e. parallelism between groups of instructions
    • G06F8/456—Parallelism detection
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/45—Exploiting coarse grain parallelism in compilation, i.e. parallelism between groups of instructions
    • G06F8/458—Synchronisation, e.g. post-wait, barriers, locks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5061—Partitioning or combining of resources
    • G06F9/5066—Algorithms for mapping a plurality of inter-dependent sub-tasks onto a plurality of physical CPUs

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Stored Programmes (AREA)
  • Devices For Executing Special Programs (AREA)

Abstract

Procédé élémentaire d’implémentation d’un module logiciel défini par un graphe élémentaire (Ge) orienté non cyclique, comprenant les étapes suivantes : copie du code de la séquence initiale (Si), ajout, en fin de la séquence initiale (Si), d’une fonction Fourche (F), copie du code d’une séquence parallèle (S1p, S2p), ajout en fin de ladite séquence parallèle (S1p, S2p) d’une fonction Jonction Drapeau (Jf), copie du code de l’autre séquence parallèle (S2p, S1p), ajout en fin de l’autre séquence parallèle (S2p, S1p) d’une fonction Jonction Attente (Jw). Figure d’abrégé : Figure 4
FR2103153A 2021-03-29 2021-03-29 Procédé d’implémentation d’un module logiciel défini par un graphe orienté non cyclique non imbriqué en environnement multi-cœur Active FR3121249B1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
FR2103153A FR3121249B1 (fr) 2021-03-29 2021-03-29 Procédé d’implémentation d’un module logiciel défini par un graphe orienté non cyclique non imbriqué en environnement multi-cœur
CN202280025557.3A CN117099080A (zh) 2021-03-29 2022-03-23 在多核环境中实现由不交错的有向无环图定义的软件模块的方法
US18/276,947 US20240118879A1 (en) 2021-03-29 2022-03-23 Method for implementing a software module defined by a non-interleaved directed acyclic graph in a multicore environment
PCT/EP2022/057593 WO2022207424A1 (fr) 2021-03-29 2022-03-23 Procede d'implementation d'un module logiciel defini par un graphe oriente non cyclique non imbrique en environnement multi-cœur

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR2103153 2021-03-29
FR2103153A FR3121249B1 (fr) 2021-03-29 2021-03-29 Procédé d’implémentation d’un module logiciel défini par un graphe orienté non cyclique non imbriqué en environnement multi-cœur

Publications (2)

Publication Number Publication Date
FR3121249A1 FR3121249A1 (fr) 2022-09-30
FR3121249B1 true FR3121249B1 (fr) 2024-03-08

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Application Number Title Priority Date Filing Date
FR2103153A Active FR3121249B1 (fr) 2021-03-29 2021-03-29 Procédé d’implémentation d’un module logiciel défini par un graphe orienté non cyclique non imbriqué en environnement multi-cœur

Country Status (4)

Country Link
US (1) US20240118879A1 (fr)
CN (1) CN117099080A (fr)
FR (1) FR3121249B1 (fr)
WO (1) WO2022207424A1 (fr)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8495636B2 (en) * 2007-12-19 2013-07-23 International Business Machines Corporation Parallelizing single threaded programs by performing look ahead operation on the single threaded program to identify plurality of instruction threads prior to execution
US9747108B2 (en) * 2015-03-27 2017-08-29 Intel Corporation User-level fork and join processors, methods, systems, and instructions

Also Published As

Publication number Publication date
CN117099080A (zh) 2023-11-21
US20240118879A1 (en) 2024-04-11
WO2022207424A1 (fr) 2022-10-06
FR3121249A1 (fr) 2022-09-30

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