FR3109243B1 - Transistor characterization process for attenuating irradiation effects on an integrated circuit manufactured using SOI technology. - Google Patents

Transistor characterization process for attenuating irradiation effects on an integrated circuit manufactured using SOI technology. Download PDF

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Publication number
FR3109243B1
FR3109243B1 FR2003654A FR2003654A FR3109243B1 FR 3109243 B1 FR3109243 B1 FR 3109243B1 FR 2003654 A FR2003654 A FR 2003654A FR 2003654 A FR2003654 A FR 2003654A FR 3109243 B1 FR3109243 B1 FR 3109243B1
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France
Prior art keywords
attenuating
temperature
heating
integrated circuit
values
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR2003654A
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French (fr)
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FR3109243A1 (en
Inventor
Alejandro Urena-Acuna
Jean-Marc Armani
Mariem Slimani
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Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
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Priority to FR2003654A priority Critical patent/FR3109243B1/en
Publication of FR3109243A1 publication Critical patent/FR3109243A1/en
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Publication of FR3109243B1 publication Critical patent/FR3109243B1/en
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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2607—Circuits therefor
    • G01R31/2621—Circuits therefor for testing field effect transistors, i.e. FET's
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/2605—Bombardment with radiation using natural radiation, e.g. alpha, beta or gamma radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/326—Application of electric currents or fields, e.g. for electroforming

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

Procédé de caractérisation de transistors SOI destiné à déterminer au moins un couple d’une tension électrique et d’une température à appliquer pour atténuer les effets des radiations sur les transistors ; le procédé comprenant les étapes : mesurer une courbe initiale caractéristique (Id - Vg)0 du fonctionnement du transistor, exposer l’échantillon à des radiations pour atteindre une dose absorbée prédéterminée, pour chaque valeur de tension électrique prise parmi une pluralité de valeurs, appliquer la valeur de tension électrique (Vbg)i et réitérer la première étape pour obtenir une nouvelle courbe caractéristique, chauffer l’échantillon à une température de chauffe pendant une durée déterminée, répéter les étapes de mesure et de chauffe en faisant varier la température de chauffe par valeurs croissantes, comparer au moins une nouvelle courbe obtenue avec la courbe initiale pour déterminer au moins un couple de valeurs de température et tension (Topt, Vbg_opt)n respectant un critère de variation. Figure pour l’abrégé : Fig. 4Method for characterizing SOI transistors intended to determine at least a couple of an electric voltage and a temperature to be applied to attenuate the effects of radiation on the transistors; the method comprising the steps of: measuring an initial curve characteristic (Id - Vg)0 of the operation of the transistor, exposing the sample to radiation to achieve a predetermined absorbed dose, for each value of electrical voltage taken from a plurality of values, applying the electrical voltage value (Vbg)i and repeating the first step to obtain a new characteristic curve, heating the sample at a heating temperature for a determined time, repeating the measurement and heating steps by varying the heating temperature by increasing values, comparing at least one new curve obtained with the initial curve to determine at least one pair of temperature and voltage values (Topt, Vbg_opt)n respecting a variation criterion. Figure for the abstract: Fig. 4

FR2003654A 2020-04-10 2020-04-10 Transistor characterization process for attenuating irradiation effects on an integrated circuit manufactured using SOI technology. Active FR3109243B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR2003654A FR3109243B1 (en) 2020-04-10 2020-04-10 Transistor characterization process for attenuating irradiation effects on an integrated circuit manufactured using SOI technology.

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR2003654 2020-04-10
FR2003654A FR3109243B1 (en) 2020-04-10 2020-04-10 Transistor characterization process for attenuating irradiation effects on an integrated circuit manufactured using SOI technology.

Publications (2)

Publication Number Publication Date
FR3109243A1 FR3109243A1 (en) 2021-10-15
FR3109243B1 true FR3109243B1 (en) 2022-04-08

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FR2003654A Active FR3109243B1 (en) 2020-04-10 2020-04-10 Transistor characterization process for attenuating irradiation effects on an integrated circuit manufactured using SOI technology.

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FR (1) FR3109243B1 (en)

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5516731A (en) * 1994-06-02 1996-05-14 Lsi Logic Corporation High-temperature bias anneal of integrated circuits for improved radiation hardness and hot electron resistance
JP2002269972A (en) 2000-12-27 2002-09-20 Seiko Epson Corp Semiconductor memory, and operating method for memory cell consisting of ferroelectric capacitors
US9030328B2 (en) * 2012-10-10 2015-05-12 Siemens Aktiengsellschaft Integrated circuit to operate in an area of ionizing radiation, and having an output for a radiation dose-dependent way damage information, and alarm indicators and corresponding method
US9064824B2 (en) 2013-11-12 2015-06-23 International Business Machines Corporation In-situ annealing for extending the lifetime of CMOS products
US10551423B1 (en) * 2015-01-13 2020-02-04 The United States Of America As Represented By The Secretary Of The Army System and method for simultaneous testing of radiation, environmental and electrical reliability of multiple semiconductor electrical devices
FR3069126B1 (en) * 2017-07-12 2020-11-13 Commissariat Energie Atomique DEVICE FOR REGENERATION OF ELECTRONIC COMPONENTS IN A NUCLEAR ENVIRONMENT
CN110596560B (en) * 2018-05-25 2020-07-28 北京大学 Method for evaluating total dose radiation effect of FinFET (Fin field effect transistor) device
CN108511402B (en) 2018-05-31 2019-12-06 西北核技术研究所 temperature-based radiation-resistant reinforcing method for CMOS (complementary Metal oxide semiconductor) process device

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Publication number Publication date
FR3109243A1 (en) 2021-10-15

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