FR3105569B1 - Procédé de collage de puces à un substrat par collage direct - Google Patents

Procédé de collage de puces à un substrat par collage direct Download PDF

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Publication number
FR3105569B1
FR3105569B1 FR1914956A FR1914956A FR3105569B1 FR 3105569 B1 FR3105569 B1 FR 3105569B1 FR 1914956 A FR1914956 A FR 1914956A FR 1914956 A FR1914956 A FR 1914956A FR 3105569 B1 FR3105569 B1 FR 3105569B1
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France
Prior art keywords
chips
bonding
substrate
contact
liquid film
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FR1914956A
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English (en)
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FR3105569A1 (fr
Inventor
Frank Fournel
Loic Sanchez
Brigitte Montmayeul
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Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
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Priority to FR1914956A priority Critical patent/FR3105569B1/fr
Application filed by Commissariat a lEnergie Atomique CEA, Commissariat a lEnergie Atomique et aux Energies Alternatives CEA filed Critical Commissariat a lEnergie Atomique CEA
Priority to EP20823879.0A priority patent/EP4078663A1/fr
Priority to CN202080096933.9A priority patent/CN115136287A/zh
Priority to US17/786,000 priority patent/US20230029338A1/en
Priority to PCT/EP2020/086664 priority patent/WO2021122909A1/fr
Priority to CA3161399A priority patent/CA3161399A1/fr
Priority to JP2022537366A priority patent/JP2023508867A/ja
Publication of FR3105569A1 publication Critical patent/FR3105569A1/fr
Application granted granted Critical
Publication of FR3105569B1 publication Critical patent/FR3105569B1/fr
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Die Bonding (AREA)
  • Wire Bonding (AREA)
  • Adhesives Or Adhesive Processes (AREA)

Abstract

Le procédé de collage de puces (100) à un substrat (101) par collage direct comporte une étape de fourniture d’un support (105) avec lequel les puces (100) sont en contact, les puces (100) en contact avec le support (105) étant individualisées. Ce procédé de collage comporte :- une étape de formation d’un film (103) liquide sur une face (104) du substrat (101),- une étape de mise en contact des puces (100) avec le film (103) liquide, la mise en contact des puces (100) avec le film (103) liquide provoquant une attraction des puces (100) vers le substrat (101),- une étape d’évaporation du film (103) liquide pour coller les puces (100) au substrat (101) par collage direct. Figure à publier avec l’abrégé : Fig. 8
FR1914956A 2019-12-19 2019-12-19 Procédé de collage de puces à un substrat par collage direct Active FR3105569B1 (fr)

Priority Applications (7)

Application Number Priority Date Filing Date Title
FR1914956A FR3105569B1 (fr) 2019-12-19 2019-12-19 Procédé de collage de puces à un substrat par collage direct
CN202080096933.9A CN115136287A (zh) 2019-12-19 2020-12-17 通过直接键合将芯片键合到基板的方法
US17/786,000 US20230029338A1 (en) 2019-12-19 2020-12-17 Method for bonding chips to a substrate by direct bonding
PCT/EP2020/086664 WO2021122909A1 (fr) 2019-12-19 2020-12-17 Procédé de collage de puces à un substrat par collage direct
EP20823879.0A EP4078663A1 (fr) 2019-12-19 2020-12-17 Procédé de collage de puces à un substrat par collage direct
CA3161399A CA3161399A1 (fr) 2019-12-19 2020-12-17 Procede de collage de puces a un substrat par collage direct
JP2022537366A JP2023508867A (ja) 2019-12-19 2020-12-17 ダイレクトボンディングによる基板への複数のチップの接合方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1914956 2019-12-19
FR1914956A FR3105569B1 (fr) 2019-12-19 2019-12-19 Procédé de collage de puces à un substrat par collage direct

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FR3105569A1 FR3105569A1 (fr) 2021-06-25
FR3105569B1 true FR3105569B1 (fr) 2021-12-17

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US (1) US20230029338A1 (fr)
EP (1) EP4078663A1 (fr)
JP (1) JP2023508867A (fr)
CN (1) CN115136287A (fr)
CA (1) CA3161399A1 (fr)
FR (1) FR3105569B1 (fr)
WO (1) WO2021122909A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3131469A1 (fr) 2021-12-23 2023-06-30 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procédé d’assemblage par collage direct de composants électroniques

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040154733A1 (en) * 2001-02-08 2004-08-12 Thomas Morf Chip transfer method and apparatus
WO2006077739A1 (fr) * 2004-12-28 2006-07-27 Mitsumasa Koyanagi Méthode et appareil de fabrication de dispositif à circuit intégré utilisant une fonction d’auto-organisation
EP3590130A1 (fr) * 2017-03-02 2020-01-08 EV Group E. Thallner GmbH Procédé et dispositif d'assemblage de puces
US10217718B1 (en) * 2017-10-13 2019-02-26 Denselight Semiconductors Pte. Ltd. Method for wafer-level semiconductor die attachment

Also Published As

Publication number Publication date
JP2023508867A (ja) 2023-03-06
FR3105569A1 (fr) 2021-06-25
CN115136287A (zh) 2022-09-30
US20230029338A1 (en) 2023-01-26
EP4078663A1 (fr) 2022-10-26
CA3161399A1 (fr) 2021-06-24
WO2021122909A1 (fr) 2021-06-24

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