FR3083638B1 - Circuit de memorisation en logique adiabatique capacitive - Google Patents

Circuit de memorisation en logique adiabatique capacitive Download PDF

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Publication number
FR3083638B1
FR3083638B1 FR1856243A FR1856243A FR3083638B1 FR 3083638 B1 FR3083638 B1 FR 3083638B1 FR 1856243 A FR1856243 A FR 1856243A FR 1856243 A FR1856243 A FR 1856243A FR 3083638 B1 FR3083638 B1 FR 3083638B1
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France
Prior art keywords
terminal
capacitive
loop
cells
adiabatic logic
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FR1856243A
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FR3083638A1 (fr
Inventor
Yann Perrin
Gael Pillonnet
Herve Fanet
Ayrat Galisultanov
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Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
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Commissariat a lEnergie Atomique CEA
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
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Priority to FR1856243A priority Critical patent/FR3083638B1/fr
Publication of FR3083638A1 publication Critical patent/FR3083638A1/fr
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0019—Arrangements for reducing power consumption by energy recovery or adiabatic operation

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

La présente description concerne un circuit de mémorisation en logique adiabatique capacitive, comportant un nombre entier k supérieur ou égal à 2 de cellules logiques (F1, B2, B3, B4) comportant chacune une première borne d'entrée principale (el), une borne de sortie (s1) et une borne d'alimentation (al), les cellules étant reliées en boucle de façon que chaque cellule ait sa première borne d'entrée principale (el) reliée à la borne de sortie (s1) de la cellule précédente de la boucle, et chaque cellule recevant sur sa borne d'alimentation (al) une tension variable périodique d'alimentation, les tensions d'alimentation des k cellules de la boucle étant déphasées deux à deux d'environ 2π/k.
FR1856243A 2018-07-06 2018-07-06 Circuit de memorisation en logique adiabatique capacitive Active FR3083638B1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR1856243A FR3083638B1 (fr) 2018-07-06 2018-07-06 Circuit de memorisation en logique adiabatique capacitive

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1856243 2018-07-06
FR1856243A FR3083638B1 (fr) 2018-07-06 2018-07-06 Circuit de memorisation en logique adiabatique capacitive

Publications (2)

Publication Number Publication Date
FR3083638A1 FR3083638A1 (fr) 2020-01-10
FR3083638B1 true FR3083638B1 (fr) 2020-09-25

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FR1856243A Active FR3083638B1 (fr) 2018-07-06 2018-07-06 Circuit de memorisation en logique adiabatique capacitive

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FR (1) FR3083638B1 (fr)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4021788A (en) * 1975-05-16 1977-05-03 Burroughs Corporation Capacitor memory cell
CA2151850A1 (fr) * 1994-07-18 1996-01-19 Thaddeus John Gabara Porte adiobatique utilisant plusieurs signaux d'horloge a phases differentes
JP3683888B2 (ja) * 1997-09-05 2005-08-17 日本電信電話株式会社 断熱充電論理回路
FR3045982B1 (fr) 2015-12-18 2019-06-14 Commissariat A L'energie Atomique Et Aux Energies Alternatives Cellule logique a faible consommation

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Publication number Publication date
FR3083638A1 (fr) 2020-01-10

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