FR3081251B1 - Dispositif d'affichage permettant de traiter un double signal d'entree - Google Patents

Dispositif d'affichage permettant de traiter un double signal d'entree Download PDF

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Publication number
FR3081251B1
FR3081251B1 FR1854079A FR1854079A FR3081251B1 FR 3081251 B1 FR3081251 B1 FR 3081251B1 FR 1854079 A FR1854079 A FR 1854079A FR 1854079 A FR1854079 A FR 1854079A FR 3081251 B1 FR3081251 B1 FR 3081251B1
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France
Prior art keywords
control block
display device
control
processing
input signal
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Active
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FR1854079A
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English (en)
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FR3081251A1 (fr
Inventor
Gunther Haas
Laurent CHARRIER
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MICROOLED
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MICROOLED
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Publication date
Priority to FR1854079A priority Critical patent/FR3081251B1/fr
Application filed by MICROOLED filed Critical MICROOLED
Priority to JP2020564480A priority patent/JP7478671B2/ja
Priority to PCT/FR2019/051100 priority patent/WO2019220055A1/fr
Priority to CN201980031461.6A priority patent/CN112106130B/zh
Priority to KR1020207036135A priority patent/KR102658293B1/ko
Priority to EP19737162.8A priority patent/EP3794578A1/fr
Priority to US17/050,477 priority patent/US11514841B2/en
Publication of FR3081251A1 publication Critical patent/FR3081251A1/fr
Application granted granted Critical
Publication of FR3081251B1 publication Critical patent/FR3081251B1/fr
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Classifications

    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00Aspects of the constitution of display devices
    • G09G2300/08Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809Several active elements per pixel in active matrix panels
    • G09G2300/0842Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00Aspects of the constitution of display devices
    • G09G2300/08Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809Several active elements per pixel in active matrix panels
    • G09G2300/0842Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0857Static memory circuit, e.g. flip-flop
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00Aspects of display data processing
    • G09G2340/12Overlay of images, i.e. displayed pixel being the result of switching between the corresponding input pixels
    • G09G2340/125Overlay of images, i.e. displayed pixel being the result of switching between the corresponding input pixels wherein one of the images is motion video

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

Dispositif d'affichage électroluminesecent (1) comprenant - Une matrice de pixels électroluminescents (38) formée d'une pluralité de pixels déposés sur un substrat, selon un arrangement matriciel en lignes et colonnes, chaque pixel étant formé d'au moins une zone émettrice élementaire (225,325,425) ; - un premier bloc de contrôle (2) configuré pour contrôler un flux de données graphiques et/ou alphanumériques capable de s'afficher sur ladite matrice de pixels (38) ; - un second bloc de contrôle (3) configuré pour contrôler un flux de données vidéo capable de s'afficher sur ladite matrice de pixels (38); - une unité (4) de génération d'une tension de référence, caractérisé en ce que : - chaque zone émettrice élémentaire est reliée à une mémoire statique, adressée par ledit premier bloc de contrôle (2), et à une mémoire dynamique, adressée par ledit second bloc de contrôle (3) ; - ledit premier (2) et deuxième (3) bloc de contrôle sont configurés pour pouvoir afficher alternativement ou simultanément des données sur la même matrice de pixels (38).
FR1854079A 2018-05-16 2018-05-16 Dispositif d'affichage permettant de traiter un double signal d'entree Active FR3081251B1 (fr)

Priority Applications (7)

Application Number Priority Date Filing Date Title
FR1854079A FR3081251B1 (fr) 2018-05-16 2018-05-16 Dispositif d'affichage permettant de traiter un double signal d'entree
PCT/FR2019/051100 WO2019220055A1 (fr) 2018-05-16 2019-05-15 Dispositif d'affichage permettant de traiter un double signal d'entree
CN201980031461.6A CN112106130B (zh) 2018-05-16 2019-05-15 用于处理双输入信号的显示单元
KR1020207036135A KR102658293B1 (ko) 2018-05-16 2019-05-15 이중 입력 신호 처리를 위한 디스플레이 유닛
JP2020564480A JP7478671B2 (ja) 2018-05-16 2019-05-15 二重入力信号を処理するための表示部
EP19737162.8A EP3794578A1 (fr) 2018-05-16 2019-05-15 Dispositif d'affichage permettant de traiter un double signal d'entree
US17/050,477 US11514841B2 (en) 2018-05-16 2019-05-15 Visual display unit for processing a double input signal

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1854079A FR3081251B1 (fr) 2018-05-16 2018-05-16 Dispositif d'affichage permettant de traiter un double signal d'entree
FR1854079 2018-05-16

Publications (2)

Publication Number Publication Date
FR3081251A1 FR3081251A1 (fr) 2019-11-22
FR3081251B1 true FR3081251B1 (fr) 2020-06-05

Family

ID=63834089

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1854079A Active FR3081251B1 (fr) 2018-05-16 2018-05-16 Dispositif d'affichage permettant de traiter un double signal d'entree

Country Status (7)

Country Link
US (1) US11514841B2 (fr)
EP (1) EP3794578A1 (fr)
JP (1) JP7478671B2 (fr)
KR (1) KR102658293B1 (fr)
CN (1) CN112106130B (fr)
FR (1) FR3081251B1 (fr)
WO (1) WO2019220055A1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11626153B2 (en) * 2021-06-07 2023-04-11 Omnivision Technologies, Inc. Low power static random-access memory
CN115512651B (zh) * 2022-11-22 2023-04-14 苏州珂晶达电子有限公司 一种微显示无源阵列的显示驱动***及方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1285258B1 (it) * 1996-02-26 1998-06-03 Cselt Centro Studi Lab Telecom Dispositivo di manipolazione di sequenze video compresse.
JP3261519B2 (ja) * 1996-06-11 2002-03-04 株式会社日立製作所 液晶表示装置
US5952991A (en) * 1996-11-14 1999-09-14 Kabushiki Kaisha Toshiba Liquid crystal display
US6597329B1 (en) * 1999-01-08 2003-07-22 Intel Corporation Readable matrix addressable display system
JP4552069B2 (ja) * 2001-01-04 2010-09-29 株式会社日立製作所 画像表示装置およびその駆動方法
TW536689B (en) * 2001-01-18 2003-06-11 Sharp Kk Display, portable device, and substrate
JP2002351430A (ja) * 2001-05-30 2002-12-06 Mitsubishi Electric Corp 表示装置
JP3603832B2 (ja) * 2001-10-19 2004-12-22 ソニー株式会社 液晶表示装置およびこれを用いた携帯端末装置
JP3798370B2 (ja) * 2001-11-29 2006-07-19 株式会社半導体エネルギー研究所 表示装置及びこれを用いた表示システム
EP1388842B1 (fr) * 2002-08-09 2013-10-02 Semiconductor Energy Laboratory Co., Ltd. Dispositif de visualisation à fenêtres multiples et son procédé de commande
JP5270120B2 (ja) * 2007-07-25 2013-08-21 グローバル・オーエルイーディー・テクノロジー・リミテッド・ライアビリティ・カンパニー デュアルディスプレイ装置
JP5086766B2 (ja) * 2007-10-18 2012-11-28 グローバル・オーエルイーディー・テクノロジー・リミテッド・ライアビリティ・カンパニー 表示装置
US8502758B2 (en) * 2009-12-10 2013-08-06 Young Electric Sign Company Apparatus and method for mapping virtual pixels to physical light elements of a display
US10102828B2 (en) 2013-01-09 2018-10-16 Nxp Usa, Inc. Method and apparatus for adaptive graphics compression and display buffer switching
KR102034055B1 (ko) * 2013-03-19 2019-10-21 엘지디스플레이 주식회사 Oled 표시 장치 및 그의 구동 방법
US9653029B2 (en) * 2014-08-05 2017-05-16 Apple Inc. Concurrently refreshing multiple areas of a display device using multiple different refresh rates
US11157111B2 (en) * 2017-08-29 2021-10-26 Sony Interactive Entertainment LLC Ultrafine LED display that includes sensor elements

Also Published As

Publication number Publication date
US20210241679A1 (en) 2021-08-05
CN112106130A (zh) 2020-12-18
KR102658293B1 (ko) 2024-04-18
JP7478671B2 (ja) 2024-05-07
FR3081251A1 (fr) 2019-11-22
CN112106130B (zh) 2023-11-10
WO2019220055A1 (fr) 2019-11-21
JP2021524602A (ja) 2021-09-13
EP3794578A1 (fr) 2021-03-24
US11514841B2 (en) 2022-11-29
KR20210006992A (ko) 2021-01-19

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