FR3070090B1 - Systeme electronique et procede de fabrication d'un systeme electronique par utilisation d'un element sacrificiel - Google Patents
Systeme electronique et procede de fabrication d'un systeme electronique par utilisation d'un element sacrificiel Download PDFInfo
- Publication number
- FR3070090B1 FR3070090B1 FR1757587A FR1757587A FR3070090B1 FR 3070090 B1 FR3070090 B1 FR 3070090B1 FR 1757587 A FR1757587 A FR 1757587A FR 1757587 A FR1757587 A FR 1757587A FR 3070090 B1 FR3070090 B1 FR 3070090B1
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- Prior art keywords
- electronic system
- sacrificial element
- manufacturing
- electronic component
- connection ports
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 238000004519 manufacturing process Methods 0.000 title abstract 2
- 238000000034 method Methods 0.000 title 1
- 238000000151 deposition Methods 0.000 abstract 1
- 238000005538 encapsulation Methods 0.000 abstract 1
- 238000000926 separation method Methods 0.000 abstract 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
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- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
- H01L2224/24195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
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- H01L2224/82005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
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- H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
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- H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
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- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Manufacturing Of Electrical Connectors (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Un procédé de fabrication d'un système électronique (S) comprenant : - une étape d'application d'un élément sacrificiel (2) sur une pièce de support (1), - une étape de dépôt d'au moins un composant électronique (3) sur l'élément sacrificiel (2), - une étape de réalisation d'une pluralité d'interconnexions tridimensionnelles (5) pour former les ports de connexion du système (S) et former une couche de redistribution reliant les connecteurs (30) du composant électronique (3) aux ports de connexion du système (S), - une étape d'encapsulation afin de protéger les interconnexions tridimensionnelles (5), et - une étape de séparation du système (S) de l'élément sacrificiel (2).
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1757587A FR3070090B1 (fr) | 2017-08-08 | 2017-08-08 | Systeme electronique et procede de fabrication d'un systeme electronique par utilisation d'un element sacrificiel |
EP18748941.4A EP3665719A1 (fr) | 2017-08-08 | 2018-08-08 | Système électronique et procédé de fabrication d'un système électronique par utilisation d'un élément sacrificiel |
PCT/EP2018/071513 WO2019030286A1 (fr) | 2017-08-08 | 2018-08-08 | Systeme electronique et procede de fabrication d'un systeme electronique par utilisation d'un element sacrificiel |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1757587A FR3070090B1 (fr) | 2017-08-08 | 2017-08-08 | Systeme electronique et procede de fabrication d'un systeme electronique par utilisation d'un element sacrificiel |
FR1757587 | 2017-08-08 |
Publications (2)
Publication Number | Publication Date |
---|---|
FR3070090A1 FR3070090A1 (fr) | 2019-02-15 |
FR3070090B1 true FR3070090B1 (fr) | 2020-02-07 |
Family
ID=60765750
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR1757587A Active FR3070090B1 (fr) | 2017-08-08 | 2017-08-08 | Systeme electronique et procede de fabrication d'un systeme electronique par utilisation d'un element sacrificiel |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP3665719A1 (fr) |
FR (1) | FR3070090B1 (fr) |
WO (1) | WO2019030286A1 (fr) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP4191643A1 (fr) * | 2021-12-02 | 2023-06-07 | Nexperia B.V. | Procede de formation d'une metallisation d'interconnexion par emballage au niveau du panneau et dispositif correspondant |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5653019A (en) * | 1995-08-31 | 1997-08-05 | Regents Of The University Of California | Repairable chip bonding/interconnect process |
CN100461391C (zh) * | 2002-02-04 | 2009-02-11 | 卡西欧计算机株式会社 | 半导体装置 |
TWI233172B (en) * | 2003-04-02 | 2005-05-21 | Siliconware Precision Industries Co Ltd | Non-leaded semiconductor package and method of fabricating the same |
US7879652B2 (en) * | 2007-07-26 | 2011-02-01 | Infineon Technologies Ag | Semiconductor module |
FR2965659B1 (fr) | 2010-10-05 | 2013-11-29 | Centre Nat Rech Scient | Procédé de fabrication d'un circuit intégré |
US9502364B2 (en) | 2014-08-28 | 2016-11-22 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor package and method of forming the same |
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2017
- 2017-08-08 FR FR1757587A patent/FR3070090B1/fr active Active
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2018
- 2018-08-08 EP EP18748941.4A patent/EP3665719A1/fr active Pending
- 2018-08-08 WO PCT/EP2018/071513 patent/WO2019030286A1/fr unknown
Also Published As
Publication number | Publication date |
---|---|
WO2019030286A1 (fr) | 2019-02-14 |
FR3070090A1 (fr) | 2019-02-15 |
EP3665719A1 (fr) | 2020-06-17 |
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