FR3070090B1 - Systeme electronique et procede de fabrication d'un systeme electronique par utilisation d'un element sacrificiel - Google Patents

Systeme electronique et procede de fabrication d'un systeme electronique par utilisation d'un element sacrificiel Download PDF

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Publication number
FR3070090B1
FR3070090B1 FR1757587A FR1757587A FR3070090B1 FR 3070090 B1 FR3070090 B1 FR 3070090B1 FR 1757587 A FR1757587 A FR 1757587A FR 1757587 A FR1757587 A FR 1757587A FR 3070090 B1 FR3070090 B1 FR 3070090B1
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Prior art keywords
electronic system
sacrificial element
manufacturing
electronic component
connection ports
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FR1757587A
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FR3070090A1 (fr
Inventor
Ayad Ghannam
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3dis Tech
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3dis Tech
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Priority to FR1757587A priority Critical patent/FR3070090B1/fr
Priority to EP18748941.4A priority patent/EP3665719A1/fr
Priority to PCT/EP2018/071513 priority patent/WO2019030286A1/fr
Publication of FR3070090A1 publication Critical patent/FR3070090A1/fr
Application granted granted Critical
Publication of FR3070090B1 publication Critical patent/FR3070090B1/fr
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Manufacturing Of Electrical Connectors (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

Un procédé de fabrication d'un système électronique (S) comprenant : - une étape d'application d'un élément sacrificiel (2) sur une pièce de support (1), - une étape de dépôt d'au moins un composant électronique (3) sur l'élément sacrificiel (2), - une étape de réalisation d'une pluralité d'interconnexions tridimensionnelles (5) pour former les ports de connexion du système (S) et former une couche de redistribution reliant les connecteurs (30) du composant électronique (3) aux ports de connexion du système (S), - une étape d'encapsulation afin de protéger les interconnexions tridimensionnelles (5), et - une étape de séparation du système (S) de l'élément sacrificiel (2).
FR1757587A 2017-08-08 2017-08-08 Systeme electronique et procede de fabrication d'un systeme electronique par utilisation d'un element sacrificiel Active FR3070090B1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FR1757587A FR3070090B1 (fr) 2017-08-08 2017-08-08 Systeme electronique et procede de fabrication d'un systeme electronique par utilisation d'un element sacrificiel
EP18748941.4A EP3665719A1 (fr) 2017-08-08 2018-08-08 Système électronique et procédé de fabrication d'un système électronique par utilisation d'un élément sacrificiel
PCT/EP2018/071513 WO2019030286A1 (fr) 2017-08-08 2018-08-08 Systeme electronique et procede de fabrication d'un systeme electronique par utilisation d'un element sacrificiel

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1757587A FR3070090B1 (fr) 2017-08-08 2017-08-08 Systeme electronique et procede de fabrication d'un systeme electronique par utilisation d'un element sacrificiel
FR1757587 2017-08-08

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Publication Number Publication Date
FR3070090A1 FR3070090A1 (fr) 2019-02-15
FR3070090B1 true FR3070090B1 (fr) 2020-02-07

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FR1757587A Active FR3070090B1 (fr) 2017-08-08 2017-08-08 Systeme electronique et procede de fabrication d'un systeme electronique par utilisation d'un element sacrificiel

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EP (1) EP3665719A1 (fr)
FR (1) FR3070090B1 (fr)
WO (1) WO2019030286A1 (fr)

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EP4191643A1 (fr) * 2021-12-02 2023-06-07 Nexperia B.V. Procede de formation d'une metallisation d'interconnexion par emballage au niveau du panneau et dispositif correspondant

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Publication number Priority date Publication date Assignee Title
US5653019A (en) * 1995-08-31 1997-08-05 Regents Of The University Of California Repairable chip bonding/interconnect process
CN100461391C (zh) * 2002-02-04 2009-02-11 卡西欧计算机株式会社 半导体装置
TWI233172B (en) * 2003-04-02 2005-05-21 Siliconware Precision Industries Co Ltd Non-leaded semiconductor package and method of fabricating the same
US7879652B2 (en) * 2007-07-26 2011-02-01 Infineon Technologies Ag Semiconductor module
FR2965659B1 (fr) 2010-10-05 2013-11-29 Centre Nat Rech Scient Procédé de fabrication d'un circuit intégré
US9502364B2 (en) 2014-08-28 2016-11-22 Taiwan Semiconductor Manufacturing Company Limited Semiconductor package and method of forming the same

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