FR3069121B1 - Bascule de puce electronique numerique - Google Patents

Bascule de puce electronique numerique Download PDF

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Publication number
FR3069121B1
FR3069121B1 FR1756565A FR1756565A FR3069121B1 FR 3069121 B1 FR3069121 B1 FR 3069121B1 FR 1756565 A FR1756565 A FR 1756565A FR 1756565 A FR1756565 A FR 1756565A FR 3069121 B1 FR3069121 B1 FR 3069121B1
Authority
FR
France
Prior art keywords
alert
test chain
digital electronic
electronic chip
chip switch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR1756565A
Other languages
English (en)
Other versions
FR3069121A1 (fr
Inventor
Pascal Urard
Florian Cacho
Vincent Huard
Alok Kumar Tripathi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
STMicroelectronics Crolles 2 SAS
STMicroelectronics International NV
Original Assignee
STMicroelectronics SA
STMicroelectronics Crolles 2 SAS
STMicroelectronics International NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA, STMicroelectronics Crolles 2 SAS, STMicroelectronics International NV filed Critical STMicroelectronics SA
Priority to FR1756565A priority Critical patent/FR3069121B1/fr
Priority to US16/031,960 priority patent/US10585143B2/en
Publication of FR3069121A1 publication Critical patent/FR3069121A1/fr
Application granted granted Critical
Publication of FR3069121B1 publication Critical patent/FR3069121B1/fr
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318342—Generation of test inputs, e.g. test vectors, patterns or sequences by preliminary fault modelling, e.g. analysis, simulation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31725—Timing aspects, e.g. clock distribution, skew, propagation delay
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3177—Testing of logic operation, e.g. by logic analysers
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/31816—Soft error testing; Soft error rate evaluation; Single event testing
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318541—Scan latches or cell details
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318552—Clock circuits details
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318594—Timing aspects
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/3312—Timing analysis

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

L'invention concerne une bascule comprenant : une entrée de données (D) et une entrée (104) d'horloge (CLK) ; des entrée (TI) et sortie (TQ) de chaîne de test ; un circuit de surveillance (106) adapté à générer une alerte (F) si le temps entre l'arrivée d'une donnée et un front de l'horloge est inférieur à un seuil ; et un circuit de transmission d'alerte (204), adapté à, pendant une période de surveillance, appliquer un niveau d'alerte sur la sortie (TQ) de chaîne de test en cas d'alerte générée par le circuit de surveillance, et à appliquer le niveau d'alerte sur la sortie de chaîne de test lorsqu'un niveau d'alerte est reçu à l'entrée (TI) de chaîne de test.
FR1756565A 2017-07-11 2017-07-11 Bascule de puce electronique numerique Expired - Fee Related FR3069121B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR1756565A FR3069121B1 (fr) 2017-07-11 2017-07-11 Bascule de puce electronique numerique
US16/031,960 US10585143B2 (en) 2017-07-11 2018-07-10 Flip flop of a digital electronic chip

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1756565A FR3069121B1 (fr) 2017-07-11 2017-07-11 Bascule de puce electronique numerique
FR1756565 2017-07-11

Publications (2)

Publication Number Publication Date
FR3069121A1 FR3069121A1 (fr) 2019-01-18
FR3069121B1 true FR3069121B1 (fr) 2020-01-24

Family

ID=60382306

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1756565A Expired - Fee Related FR3069121B1 (fr) 2017-07-11 2017-07-11 Bascule de puce electronique numerique

Country Status (2)

Country Link
US (1) US10585143B2 (fr)
FR (1) FR3069121B1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113484604B (zh) * 2021-07-08 2023-04-21 中国人民解放军国防科技大学 可消除测量电路影响的set脉冲测量电路及集成电路芯片
US11680983B1 (en) 2022-02-01 2023-06-20 Nxp Usa, Inc. Integrated circuit having an in-situ circuit for detecting an impending circuit failure
US20240103066A1 (en) * 2022-09-27 2024-03-28 Infineon Technologies Ag Circuit and method for testing a circuit

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6359946B1 (en) * 1998-09-23 2002-03-19 National Instruments Corp. Clock synchronization for asynchronous data transmission
US6169501B1 (en) * 1998-09-23 2001-01-02 National Instruments Corp. Adjustable serial-to-parallel or parallel-to-serial converter
JP2002124937A (ja) * 2000-10-16 2002-04-26 Nec Corp 同期はずれ検出回路
JP2003006253A (ja) * 2001-06-20 2003-01-10 Mitsubishi Electric Corp ロジック回路設計方法およびその方法をコンピュータに実行させるプログラム
WO2011154763A1 (fr) * 2010-06-10 2011-12-15 Freescale Semiconductor, Inc. Dispositif de circuit intégré, dispositif électronique et procédé permettant de détecter les violations de synchronisation au sein d'une horloge
US8996937B2 (en) * 2011-12-28 2015-03-31 Stmicroelectronics International N.V. Apparatus for monitoring operating conditions of a logic circuit
FR2990764B1 (fr) * 2012-05-21 2015-12-11 Commissariat Energie Atomique Dispositif de test et de monitoring de circuits numeriques
US9329229B2 (en) * 2012-11-15 2016-05-03 Freescale Semiconductors, Inc. Integrated circuit with degradation monitoring
US9229051B2 (en) * 2012-11-15 2016-01-05 Freescale Semiconductor, Inc. Integrated circuit with degradation monitoring
FR3044772B1 (fr) * 2015-12-04 2018-01-05 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede pour equiper des registres d'un circuit integre pour detecter des violations temporelles

Also Published As

Publication number Publication date
US20190018062A1 (en) 2019-01-17
US10585143B2 (en) 2020-03-10
FR3069121A1 (fr) 2019-01-18

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Effective date: 20190118

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Year of fee payment: 3

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