FR3055438B1 - Compilation pour traitement parallele base sur gpu de dispositif de noeud - Google Patents

Compilation pour traitement parallele base sur gpu de dispositif de noeud Download PDF

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Publication number
FR3055438B1
FR3055438B1 FR1757193A FR1757193A FR3055438B1 FR 3055438 B1 FR3055438 B1 FR 3055438B1 FR 1757193 A FR1757193 A FR 1757193A FR 1757193 A FR1757193 A FR 1757193A FR 3055438 B1 FR3055438 B1 FR 3055438B1
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gpu
task routine
task
node device
compilation
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FR3055438A1 (fr
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Henry Gabriel Victor Bequet
Huina Chen
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SAS Institute Inc
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SAS Institute Inc
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5061—Partitioning or combining of resources
    • G06F9/5066—Algorithms for mapping a plurality of inter-dependent sub-tasks onto a plurality of physical CPUs
    • G—PHYSICS
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    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • G06F9/5044—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering hardware capabilities
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/45—Exploiting coarse grain parallelism in compilation, i.e. parallelism between groups of instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
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    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/45—Exploiting coarse grain parallelism in compilation, i.e. parallelism between groups of instructions
    • G06F8/456—Parallelism detection
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G—PHYSICS
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    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G—PHYSICS
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    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
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    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3887—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple data lanes [SIMD]
    • G—PHYSICS
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    • G06F9/44—Arrangements for executing specific programs
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    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G—PHYSICS
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    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • G06F9/5055—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering software capabilities, i.e. software resources associated or available to the machine
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5061—Partitioning or combining of resources
    • G06F9/5072—Grid computing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
    • H04L41/06—Management of faults, events, alarms or notifications
    • H04L41/0654—Management of faults, events, alarms or notifications using network fault recovery
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L67/00—Network arrangements or protocols for supporting network services or applications
    • H04L67/01—Protocols
    • H04L67/10—Protocols in which an application is distributed across nodes in the network
    • H04L67/1001—Protocols in which an application is distributed across nodes in the network for accessing one among a plurality of replicated servers
    • H04L67/1004—Server selection for load balancing
    • H04L67/1008—Server selection for load balancing based on parameters of servers, e.g. available memory or workload
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L67/00—Network arrangements or protocols for supporting network services or applications
    • H04L67/50—Network services
    • H04L67/56—Provisioning of proxy services
    • H04L67/561—Adding application-functional data or data for application control, e.g. adding metadata
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2209/00—Indexing scheme relating to G06F9/00
    • G06F2209/50—Indexing scheme relating to G06F9/50
    • G06F2209/509—Offload

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Mathematical Physics (AREA)
  • Library & Information Science (AREA)
  • Debugging And Monitoring (AREA)
  • Devices For Executing Special Programs (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
  • Multi Processors (AREA)
  • Advance Control (AREA)
  • Stored Programmes (AREA)

Abstract

Un appareil peut inclure un processeur et une mémoire pour stocker des instructions qui amènent le processeur à effectuer des opérations comprenant: en réponse à une détermination qu’un GPU d’un dispositif de nœud est disponible, déterminer si une routine de tâche peut être compilée pour générer une routine de tâche de GPU pour exécution par le GPU pour amener à la réalisation d’instances multiples d’une tâche de la routine de tâche au moins partiellement en parallèle sans dépendances entre ces dernières ; et en réponse à une détermination que la routine de tâche peut être compilée pour générer la routine de tâche de GPU : employer une règle de conversion pour convertir la routine de tâche en la routine de tâche de GPU ; compiler la routine de tâche de GPU pour exécution par le GPU ; et affecter la réalisation de la tâche avec une partition d’ensemble de données au dispositif de nœud pour permettre une réalisation des instances multiples avec la partition d’ensemble de données par le GPU.
FR1757193A 2016-08-25 2017-07-28 Compilation pour traitement parallele base sur gpu de dispositif de noeud Active FR3055438B1 (fr)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201662379512P 2016-08-25 2016-08-25
US62379512 2016-08-25
US201662394411P 2016-09-14 2016-09-14
US62394411 2016-09-14
US15/422,285 US9760376B1 (en) 2016-02-01 2017-02-01 Compilation for node device GPU-based parallel processing

Publications (2)

Publication Number Publication Date
FR3055438A1 FR3055438A1 (fr) 2018-03-02
FR3055438B1 true FR3055438B1 (fr) 2022-07-29

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FR1757193A Active FR3055438B1 (fr) 2016-08-25 2017-07-28 Compilation pour traitement parallele base sur gpu de dispositif de noeud

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CN (1) CN107783782B (fr)
BE (1) BE1025002B1 (fr)
CA (1) CA2974556C (fr)
DE (1) DE102017213160B4 (fr)
DK (1) DK179709B1 (fr)
FR (1) FR3055438B1 (fr)
GB (1) GB2553424B (fr)
HK (1) HK1245439B (fr)
NO (1) NO343250B1 (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111327921A (zh) * 2018-12-17 2020-06-23 深圳市炜博科技有限公司 视频数据处理方法及设备
CN109743453B (zh) * 2018-12-29 2021-01-05 出门问问信息科技有限公司 一种分屏显示方法及装置
CN110163791B (zh) * 2019-05-21 2020-04-17 中科驭数（北京）科技有限公司 数据计算流图的gpu处理方法及装置
CN111984322B (zh) * 2020-09-07 2023-03-24 北京航天数据股份有限公司 一种控制指令传输方法及装置
CN112783506B (zh) * 2021-01-29 2022-09-30 展讯通信（上海）有限公司 一种模型运行方法及相关装置
CN118227384A (zh) * 2024-05-24 2024-06-21 北京蓝耘科技股份有限公司 一种局域gpu数据共享方法、***及存储介质

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Publication number Priority date Publication date Assignee Title
US8134561B2 (en) * 2004-04-16 2012-03-13 Apple Inc. System for optimizing graphics operations
US8549500B2 (en) * 2007-02-14 2013-10-01 The Mathworks, Inc. Saving and loading graphical processing unit (GPU) arrays providing high computational capabilities in a computing environment
US8938723B1 (en) * 2009-08-03 2015-01-20 Parallels IP Holdings GmbH Use of GPU for support and acceleration of virtual machines and virtual environments
US8310492B2 (en) * 2009-09-03 2012-11-13 Ati Technologies Ulc Hardware-based scheduling of GPU work
US8769510B2 (en) * 2010-04-08 2014-07-01 The Mathworks, Inc. Identification and translation of program code executable by a graphical processing unit (GPU)
DE102013208418A1 (de) * 2012-05-09 2013-11-14 Nvidia Corp. Verfahren und System zur separaten Kompilierung von Geräte-Code, welcher in Host-Code eingebettet ist
US9152601B2 (en) * 2013-05-09 2015-10-06 Advanced Micro Devices, Inc. Power-efficient nested map-reduce execution on a cloud of heterogeneous accelerated processing units
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US9235871B2 (en) * 2014-02-06 2016-01-12 Oxide Interactive, LLC Method and system of a command buffer between a CPU and GPU

Also Published As

Publication number Publication date
DK201770596A1 (en) 2018-03-12
BE1025002A1 (fr) 2018-09-14
FR3055438A1 (fr) 2018-03-02
GB201712171D0 (en) 2017-09-13
CA2974556C (fr) 2018-06-05
DE102017213160A1 (de) 2018-03-01
BE1025002B1 (fr) 2018-09-17
GB2553424B (en) 2018-11-21
NO20171277A1 (en) 2018-02-26
DK179709B1 (en) 2019-04-09
NO343250B1 (en) 2018-12-27
DE102017213160B4 (de) 2023-05-25
CN107783782A (zh) 2018-03-09
HK1245439B (zh) 2019-12-06
CN107783782B (zh) 2019-03-15
GB2553424A (en) 2018-03-07
CA2974556A1 (fr) 2018-02-25

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