FR3029538B1 - Procede de transfert de couche - Google Patents

Procede de transfert de couche Download PDF

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Publication number
FR3029538B1
FR3029538B1 FR1402800A FR1402800A FR3029538B1 FR 3029538 B1 FR3029538 B1 FR 3029538B1 FR 1402800 A FR1402800 A FR 1402800A FR 1402800 A FR1402800 A FR 1402800A FR 3029538 B1 FR3029538 B1 FR 3029538B1
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FR
France
Prior art keywords
substrate
layer
intermediate layer
transfer method
heat treatment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1402800A
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English (en)
Other versions
FR3029538A1 (fr
Inventor
Vivien Renauld
Monique Lecomte
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Priority to FR1402800A priority Critical patent/FR3029538B1/fr
Priority to JP2015235008A priority patent/JP6342876B2/ja
Priority to CN201510870819.8A priority patent/CN105679699B/zh
Priority to US14/957,133 priority patent/US9583341B2/en
Priority to KR1020150171628A priority patent/KR102443270B1/ko
Publication of FR3029538A1 publication Critical patent/FR3029538A1/fr
Application granted granted Critical
Publication of FR3029538B1 publication Critical patent/FR3029538B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02694—Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/7806—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices involving the separation of the active layers from a substrate
    • H01L21/7813—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices involving the separation of the active layers from a substrate leaving a reusable substrate, e.g. epitaxial lift off
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68318—Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6835—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during build up manufacturing of active devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Optical Filters (AREA)
  • Decoration By Transfer Pictures (AREA)
  • Laminated Bodies (AREA)
  • Optical Integrated Circuits (AREA)
  • Transition And Organic Metals Composition Catalysts For Addition Polymerization (AREA)

Abstract

L'invention concerne un procédé de transfert d'une couche utile (40) comprenant les étapes : a) fournir un substrat donneur (10) comprenant une couche intermédiaire (30), un substrat support (20), une couche utile (40), la couche intermédiaire (30) est adaptée pour devenir souple ; b) fournir un substrat receveur (50) ; c) assembler le substrat receveur (50) et le substrat donneur (10) ; d) effectuer un traitement thermique du substrat receveur (50) et du substrat donneur (10), le traitement thermique étant exécuté à une seconde température supérieure à la première température ; le procédé étant caractérisé en ce que la couche intermédiaire (30) est exempte d'espèces susceptibles de dégazer, et une couche additionnelle (60) est formée, ladite couche additionnelle (60) comprenant des espèces chimiques adaptées pour diffuser dans la couche intermédiaire (30) lors de l'étape d) et y former une zone de fragilisation (31).
FR1402800A 2014-12-04 2014-12-04 Procede de transfert de couche Active FR3029538B1 (fr)

Priority Applications (5)

Application Number Priority Date Filing Date Title
FR1402800A FR3029538B1 (fr) 2014-12-04 2014-12-04 Procede de transfert de couche
JP2015235008A JP6342876B2 (ja) 2014-12-04 2015-12-01 層転写プロセス
CN201510870819.8A CN105679699B (zh) 2014-12-04 2015-12-02 层转移工艺
US14/957,133 US9583341B2 (en) 2014-12-04 2015-12-02 Layer transferring process
KR1020150171628A KR102443270B1 (ko) 2014-12-04 2015-12-03 층 전달 방법

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1402800 2014-12-04
FR1402800A FR3029538B1 (fr) 2014-12-04 2014-12-04 Procede de transfert de couche

Publications (2)

Publication Number Publication Date
FR3029538A1 FR3029538A1 (fr) 2016-06-10
FR3029538B1 true FR3029538B1 (fr) 2019-04-26

Family

ID=52450196

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1402800A Active FR3029538B1 (fr) 2014-12-04 2014-12-04 Procede de transfert de couche

Country Status (5)

Country Link
US (1) US9583341B2 (fr)
JP (1) JP6342876B2 (fr)
KR (1) KR102443270B1 (fr)
CN (1) CN105679699B (fr)
FR (1) FR3029538B1 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2995445B1 (fr) * 2012-09-07 2016-01-08 Soitec Silicon On Insulator Procede de fabrication d'une structure en vue d'une separation ulterieure
DE102018102415B4 (de) 2018-02-02 2022-09-01 Infineon Technologies Ag Waferverbund und verfahren zur herstellung eines halbleiterbauteils
DE102019102323A1 (de) * 2018-02-02 2019-08-08 Infineon Technologies Ag Waferverbund und Verfahren zur Herstellung von Halbleiterbauteilen
FR3091005B1 (fr) * 2018-12-21 2021-01-29 Soitec Silicon On Insulator Substrat de croissance et procede de fabrication d’un tel substrat
KR20220048690A (ko) 2020-10-13 2022-04-20 삼성전자주식회사 반도체 장치 제조 방법

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2681472B1 (fr) * 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
SG55413A1 (en) * 1996-11-15 1998-12-21 Method Of Manufacturing Semico Method of manufacturing semiconductor article
FR2767604B1 (fr) * 1997-08-19 2000-12-01 Commissariat Energie Atomique Procede de traitement pour le collage moleculaire et le decollage de deux structures
TW200406811A (en) * 2002-06-03 2004-05-01 Tien-Hsi Lee Transferring method of a layer onto a substrate
US6953736B2 (en) * 2002-07-09 2005-10-11 S.O.I.Tec Silicon On Insulator Technologies S.A. Process for transferring a layer of strained semiconductor material
JP4267394B2 (ja) * 2002-07-16 2009-05-27 株式会社半導体エネルギー研究所 剥離方法、及び半導体装置の作製方法
FR2844634B1 (fr) * 2002-09-18 2005-05-27 Soitec Silicon On Insulator Formation d'une couche utile relaxee a partir d'une plaquette sans couche tampon
FR2855909B1 (fr) * 2003-06-06 2005-08-26 Soitec Silicon On Insulator Procede d'obtention concomitante d'au moins une paire de structures comprenant au moins une couche utile reportee sur un substrat
US6982210B2 (en) * 2003-07-10 2006-01-03 S.O.I.Tec Silicon On Insulator Technologies S.A. Method for manufacturing a multilayer semiconductor structure that includes an irregular layer
FR2860249B1 (fr) * 2003-09-30 2005-12-09 Michel Bruel Procede de fabrication d'une structure en forme de plaque, en particulier en silicium, application de procede, et structure en forme de plaque, en particulier en silicium
FR2903808B1 (fr) * 2006-07-11 2008-11-28 Soitec Silicon On Insulator Procede de collage direct de deux substrats utilises en electronique, optique ou opto-electronique
FR2905801B1 (fr) * 2006-09-12 2008-12-05 Soitec Silicon On Insulator Procede de transfert d'une couche a haute temperature
KR101436115B1 (ko) * 2007-04-27 2014-09-01 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 기판의 제조방법, 및 반도체장치의 제조방법
CN101681807B (zh) * 2007-06-01 2012-03-14 株式会社半导体能源研究所 半导体器件的制造方法
FR2930072B1 (fr) * 2008-04-15 2010-08-20 Commissariat Energie Atomique Procede de transfert d'une couche mince par echange protonique.
EP2562789A4 (fr) * 2010-04-20 2015-03-04 Sumitomo Electric Industries Procédé de production d'un substrat composite
JP5917036B2 (ja) * 2010-08-05 2016-05-11 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法
FR2977075A1 (fr) * 2011-06-23 2012-12-28 Soitec Silicon On Insulator Procede de fabrication d'un substrat semi-conducteur, et substrat semi-conducteur

Also Published As

Publication number Publication date
CN105679699B (zh) 2020-05-22
KR102443270B1 (ko) 2022-09-14
US9583341B2 (en) 2017-02-28
JP6342876B2 (ja) 2018-06-13
FR3029538A1 (fr) 2016-06-10
US20160163535A1 (en) 2016-06-09
KR20160067778A (ko) 2016-06-14
JP2016111365A (ja) 2016-06-20
CN105679699A (zh) 2016-06-15

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