FR3001333B1 - Grille arriere dans transistor de selection pour dram embarquee - Google Patents

Grille arriere dans transistor de selection pour dram embarquee

Info

Publication number
FR3001333B1
FR3001333B1 FR1350547A FR1350547A FR3001333B1 FR 3001333 B1 FR3001333 B1 FR 3001333B1 FR 1350547 A FR1350547 A FR 1350547A FR 1350547 A FR1350547 A FR 1350547A FR 3001333 B1 FR3001333 B1 FR 3001333B1
Authority
FR
France
Prior art keywords
selection transistor
embedded dram
rear grid
grid
dram
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1350547A
Other languages
English (en)
Other versions
FR3001333A1 (fr
Inventor
Gerhard Enders
Franz Hofmann
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Priority to FR1350547A priority Critical patent/FR3001333B1/fr
Priority to CN201380070597.0A priority patent/CN104995729B/zh
Priority to SG11201505244YA priority patent/SG11201505244YA/en
Priority to KR1020157018580A priority patent/KR102148914B1/ko
Priority to US14/761,471 priority patent/US9472469B2/en
Priority to PCT/EP2013/076414 priority patent/WO2014114406A1/fr
Publication of FR3001333A1 publication Critical patent/FR3001333A1/fr
Application granted granted Critical
Publication of FR3001333B1 publication Critical patent/FR3001333B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H01L29/78648Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/01Manufacture or treatment
    • H10B12/02Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05Making the transistor
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/30DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)
FR1350547A 2013-01-22 2013-01-22 Grille arriere dans transistor de selection pour dram embarquee Active FR3001333B1 (fr)

Priority Applications (6)

Application Number Priority Date Filing Date Title
FR1350547A FR3001333B1 (fr) 2013-01-22 2013-01-22 Grille arriere dans transistor de selection pour dram embarquee
CN201380070597.0A CN104995729B (zh) 2013-01-22 2013-12-12 用于eDRAM的选择晶体管中的背栅
SG11201505244YA SG11201505244YA (en) 2013-01-22 2013-12-12 Back gate in select transistor for edram
KR1020157018580A KR102148914B1 (ko) 2013-01-22 2013-12-12 eDRAM 용 선택 트랜지스터 내의 백 게이트
US14/761,471 US9472469B2 (en) 2013-01-22 2013-12-12 Back gate in select transistor for eDRAM
PCT/EP2013/076414 WO2014114406A1 (fr) 2013-01-22 2013-12-12 Grille arrière dans un transistor de sélection pour edram

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR1350547A FR3001333B1 (fr) 2013-01-22 2013-01-22 Grille arriere dans transistor de selection pour dram embarquee

Publications (2)

Publication Number Publication Date
FR3001333A1 FR3001333A1 (fr) 2014-07-25
FR3001333B1 true FR3001333B1 (fr) 2016-05-06

Family

ID=48613740

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1350547A Active FR3001333B1 (fr) 2013-01-22 2013-01-22 Grille arriere dans transistor de selection pour dram embarquee

Country Status (6)

Country Link
US (1) US9472469B2 (fr)
KR (1) KR102148914B1 (fr)
CN (1) CN104995729B (fr)
FR (1) FR3001333B1 (fr)
SG (1) SG11201505244YA (fr)
WO (1) WO2014114406A1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11031072B2 (en) * 2017-09-28 2021-06-08 Intel Corporation Dynamic random access memory including threshold switch
CN109741777A (zh) * 2018-12-28 2019-05-10 上海新储集成电路有限公司 一种提高速度和保持数据时间的存储器
CN116206643B (zh) * 2022-07-25 2024-03-15 北京超弦存储器研究院 动态随机存储单元、存储器、存储装置及读取方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6037199A (en) * 1999-08-16 2000-03-14 Taiwan Semiconductor Manufacturing Company, Ltd. SOI device for DRAM cells beyond gigabit generation and method for making the same
DE19954867C1 (de) * 1999-11-15 2000-12-07 Infineon Technologies Ag DRAM-Zellenanordnung und Verfahren zu deren Herstellung
US6441436B1 (en) * 2000-11-29 2002-08-27 United Microelectronics Corp. SOI device and method of fabrication
US6710391B2 (en) 2002-06-26 2004-03-23 Texas Instruments Incorporated Integrated DRAM process/structure using contact pillars
KR101415509B1 (ko) * 2008-07-24 2014-07-04 삼성전자주식회사 메모리 소자, 그 제조 방법 및 동작 방법
FR2953636B1 (fr) * 2009-12-08 2012-02-10 Soitec Silicon On Insulator Procede de commande d'une cellule memoire dram sur seoi disposant d'une seconde grille de controle enterree sous la couche isolante

Also Published As

Publication number Publication date
CN104995729A (zh) 2015-10-21
US9472469B2 (en) 2016-10-18
CN104995729B (zh) 2018-04-20
KR102148914B1 (ko) 2020-08-27
FR3001333A1 (fr) 2014-07-25
US20150357333A1 (en) 2015-12-10
WO2014114406A1 (fr) 2014-07-31
KR20150110514A (ko) 2015-10-02
SG11201505244YA (en) 2015-08-28

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