FR2976403B1 - Procede de fabrication d'un circuit integre depourvu de plage de contact de masse - Google Patents
Procede de fabrication d'un circuit integre depourvu de plage de contact de masseInfo
- Publication number
- FR2976403B1 FR2976403B1 FR1155050A FR1155050A FR2976403B1 FR 2976403 B1 FR2976403 B1 FR 2976403B1 FR 1155050 A FR1155050 A FR 1155050A FR 1155050 A FR1155050 A FR 1155050A FR 2976403 B1 FR2976403 B1 FR 2976403B1
- Authority
- FR
- France
- Prior art keywords
- integrated circuit
- manufacturing
- contact range
- mass contact
- wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Dicing (AREA)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1155050A FR2976403B1 (fr) | 2011-06-09 | 2011-06-09 | Procede de fabrication d'un circuit integre depourvu de plage de contact de masse |
US13/492,504 US8741742B2 (en) | 2011-06-09 | 2012-06-08 | Method of fabricating an integrated circuit without ground contact pad |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1155050A FR2976403B1 (fr) | 2011-06-09 | 2011-06-09 | Procede de fabrication d'un circuit integre depourvu de plage de contact de masse |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2976403A1 FR2976403A1 (fr) | 2012-12-14 |
FR2976403B1 true FR2976403B1 (fr) | 2013-11-22 |
Family
ID=44550587
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR1155050A Expired - Fee Related FR2976403B1 (fr) | 2011-06-09 | 2011-06-09 | Procede de fabrication d'un circuit integre depourvu de plage de contact de masse |
Country Status (2)
Country | Link |
---|---|
US (1) | US8741742B2 (fr) |
FR (1) | FR2976403B1 (fr) |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5047711A (en) * | 1989-08-23 | 1991-09-10 | Silicon Connections Corporation | Wafer-level burn-in testing of integrated circuits |
US5442282A (en) * | 1992-07-02 | 1995-08-15 | Lsi Logic Corporation | Testing and exercising individual, unsingulated dies on a wafer |
JPH07169807A (ja) * | 1993-12-16 | 1995-07-04 | Nippondenso Co Ltd | 半導体ウェハ |
TW396480B (en) * | 1994-12-19 | 2000-07-01 | Matsushita Electric Ind Co Ltd | Semiconductor chip and semiconductor wafer with power pads used for probing test |
US6064116A (en) * | 1997-06-06 | 2000-05-16 | Micron Technology, Inc. | Device for electrically or thermally coupling to the backsides of integrated circuit dice in chip-on-board applications |
US6355950B1 (en) * | 1998-09-23 | 2002-03-12 | Intel Corporation | Substrate interconnect for power distribution on integrated circuits |
KR100462980B1 (ko) * | 1999-09-13 | 2004-12-23 | 비쉐이 메저먼츠 그룹, 인코포레이티드 | 반도체장치용 칩 스케일 표면 장착 패키지 및 그 제조공정 |
US7173444B2 (en) * | 2000-04-04 | 2007-02-06 | Ali Pourkeramati | Structure and method for parallel testing of dies on a semiconductor wafer |
US6664608B1 (en) * | 2001-11-30 | 2003-12-16 | Sun Microsystems, Inc. | Back-biased MOS device |
US7026646B2 (en) * | 2002-06-20 | 2006-04-11 | Micron Technology, Inc. | Isolation circuit |
CN101273454B (zh) * | 2005-09-27 | 2010-06-23 | Nxp股份有限公司 | 划线通道中具有用于管芯测试的元件的晶片 |
JP2008021848A (ja) * | 2006-07-13 | 2008-01-31 | Sharp Corp | ウェハおよび半導体装置のテスト方法 |
-
2011
- 2011-06-09 FR FR1155050A patent/FR2976403B1/fr not_active Expired - Fee Related
-
2012
- 2012-06-08 US US13/492,504 patent/US8741742B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US8741742B2 (en) | 2014-06-03 |
US20120313223A1 (en) | 2012-12-13 |
FR2976403A1 (fr) | 2012-12-14 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |
Effective date: 20150227 |