FR2973149B1 - Architecture de memoire logique, notamment pour mram ou pcram ou rram. - Google Patents

Architecture de memoire logique, notamment pour mram ou pcram ou rram. Download PDF

Info

Publication number
FR2973149B1
FR2973149B1 FR1152472A FR1152472A FR2973149B1 FR 2973149 B1 FR2973149 B1 FR 2973149B1 FR 1152472 A FR1152472 A FR 1152472A FR 1152472 A FR1152472 A FR 1152472A FR 2973149 B1 FR2973149 B1 FR 2973149B1
Authority
FR
France
Prior art keywords
cells
column
component
relates
writing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1152472A
Other languages
English (en)
Other versions
FR2973149A1 (fr
Inventor
Weisheng Zhao
Sumanta Chaudhuri
Claude Chappert
Jacques-Olivier Klein
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Universite Paris Saclay
Original Assignee
Universite Paris Sud Paris 11
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Universite Paris Sud Paris 11 filed Critical Universite Paris Sud Paris 11
Priority to FR1152472A priority Critical patent/FR2973149B1/fr
Priority to PCT/FR2012/050617 priority patent/WO2012168591A1/fr
Priority to US14/007,017 priority patent/US9305607B2/en
Priority to EP12717374.8A priority patent/EP2689422A1/fr
Publication of FR2973149A1 publication Critical patent/FR2973149A1/fr
Application granted granted Critical
Publication of FR2973149B1 publication Critical patent/FR2973149B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1653—Address circuits or decoders
    • G11C11/1655—Bit-line or column circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1659—Cell access
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1673—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1675—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/77—Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Mram Or Spin Memory Techniques (AREA)
  • Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)

Abstract

La présente invention concerne une architecture et un procédé de lecture en parallèle et d'écriture en parallèle ou en série d'un composant électronique de mémoire basé sur une matrice bidimensionnelle de cellules unitaires de mémoire binaire à deux bornes, intégrées au sein d'une architecture de type « crossbar ». Selon l'invention, ce composant comporte des moyens logiques de sélection de colonne extérieurs à la matrice, qui activent au moins une colonne dont une ou plusieurs cellules doivent subir un traitement de lecture ou écriture. Elle concerne aussi un tel composant et procédé avec lecture de l'état des cellules par détection différentielle à partir de deux cellules de deux rangées différentes, soit entre une colonne de stockage et une colonne de référence constante, soit entre deux rangées ou deux colonnes de stockage se correspondant deux à deux. L'invention concerne aussi un tel composant dans lequel certains moyens de sélection sont dédiés exclusivement à des opérations de lecture, et/ou dans lequel des cellules complémentaires dans deux colonnes complémentaires connectées entre elles sont encodées en une seule opération atomique par un même courant d'écriture.
FR1152472A 2011-03-24 2011-03-24 Architecture de memoire logique, notamment pour mram ou pcram ou rram. Active FR2973149B1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
FR1152472A FR2973149B1 (fr) 2011-03-24 2011-03-24 Architecture de memoire logique, notamment pour mram ou pcram ou rram.
PCT/FR2012/050617 WO2012168591A1 (fr) 2011-03-24 2012-03-23 Architecture de memoire logique, notamment pour mram ou pcram ou rram
US14/007,017 US9305607B2 (en) 2011-03-24 2012-03-23 Logical memory architecture, in particular for MRAM, PCRAM, or RRAM
EP12717374.8A EP2689422A1 (fr) 2011-03-24 2012-03-23 Architecture de memoire logique, notamment pour mram ou pcram ou rram

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR1152472A FR2973149B1 (fr) 2011-03-24 2011-03-24 Architecture de memoire logique, notamment pour mram ou pcram ou rram.

Publications (2)

Publication Number Publication Date
FR2973149A1 FR2973149A1 (fr) 2012-09-28
FR2973149B1 true FR2973149B1 (fr) 2021-12-10

Family

ID=46017938

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1152472A Active FR2973149B1 (fr) 2011-03-24 2011-03-24 Architecture de memoire logique, notamment pour mram ou pcram ou rram.

Country Status (4)

Country Link
US (1) US9305607B2 (fr)
EP (1) EP2689422A1 (fr)
FR (1) FR2973149B1 (fr)
WO (1) WO2012168591A1 (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ITTO20120682A1 (it) * 2012-07-31 2014-02-01 St Microelectronics Pvt Ltd Dispositivo di memoria non volatile con celle raggruppate
WO2018005572A1 (fr) 2016-06-30 2018-01-04 University Of Pittsburgh-Of The Commonwealth System Of Higher Education Mémoire non volatile accessible en deux dimensions
CN107591180A (zh) * 2016-07-07 2018-01-16 中芯国际集成电路制造(上海)有限公司 非挥发性存储器及其读取数据的方法
US10283190B1 (en) 2017-12-18 2019-05-07 Qualcomm Incorporated Transpose non-volatile (NV) memory (NVM) bit cells and related data arrays configured for row and column, transpose access operations
WO2021142681A1 (fr) * 2020-01-15 2021-07-22 华为技术有限公司 Mémoire vive magnétique et dispositif électronique
EP4092674A1 (fr) 2021-05-19 2022-11-23 Commissariat à l'Energie Atomique et aux Energies Alternatives Circuit de programmation de mémoire non volatile et procédé de programmation de dispositifs de mémoire non volatile

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5640343A (en) 1996-03-18 1997-06-17 International Business Machines Corporation Magnetic memory array using magnetic tunnel junction devices in the memory cells
US6055178A (en) * 1998-12-18 2000-04-25 Motorola, Inc. Magnetic random access memory with a reference memory array
US6418046B1 (en) * 2001-01-30 2002-07-09 Motorola, Inc. MRAM architecture and system
JP4637388B2 (ja) * 2001-03-23 2011-02-23 ルネサスエレクトロニクス株式会社 薄膜磁性体記憶装置
US6795336B2 (en) 2001-12-07 2004-09-21 Hynix Semiconductor Inc. Magnetic random access memory
DE60227907D1 (de) 2001-12-21 2008-09-11 Toshiba Kk Magnetischer Direktzugriffsspeicher
US7272035B1 (en) * 2005-08-31 2007-09-18 Grandis, Inc. Current driven switching of magnetic storage cells utilizing spin transfer and magnetic memories using such cells
JP5193419B2 (ja) * 2005-10-28 2013-05-08 株式会社東芝 スピン注入磁気ランダムアクセスメモリとその書き込み方法
JP4855821B2 (ja) * 2006-04-12 2012-01-18 株式会社東芝 磁気記憶装置
JP2008217844A (ja) * 2007-02-28 2008-09-18 Matsushita Electric Ind Co Ltd 不揮発性半導体記憶装置
KR100919565B1 (ko) * 2007-07-24 2009-10-01 주식회사 하이닉스반도체 상 변화 메모리 장치
US7764536B2 (en) 2007-08-07 2010-07-27 Grandis, Inc. Method and system for providing a sense amplifier and drive circuit for spin transfer torque magnetic random access memory
JP4482039B2 (ja) * 2008-01-11 2010-06-16 株式会社東芝 抵抗変化型メモリ
US7715228B2 (en) 2008-08-25 2010-05-11 Nve Corporation Cross-point magnetoresistive memory
US7936580B2 (en) * 2008-10-20 2011-05-03 Seagate Technology Llc MRAM diode array and access method
JP5214560B2 (ja) * 2009-08-19 2013-06-19 株式会社東芝 不揮発性半導体記憶装置

Also Published As

Publication number Publication date
US9305607B2 (en) 2016-04-05
EP2689422A1 (fr) 2014-01-29
WO2012168591A1 (fr) 2012-12-13
US20140016390A1 (en) 2014-01-16
FR2973149A1 (fr) 2012-09-28

Similar Documents

Publication Publication Date Title
FR2973149B1 (fr) Architecture de memoire logique, notamment pour mram ou pcram ou rram.
TWI705444B (zh) 運算記憶體之架構
Jost et al. Uranium isotope evidence for an expansion of marine anoxia during the end‐T riassic extinction
Sallan et al. Persistent predator–prey dynamics revealed by mass extinction
JP6120911B2 (ja) 揮発性スイッチング二端子装置およびｍｏｓトランジスタを利用した不揮発性メモリセル
Newberry et al. Tightly bound soil water introduces isotopic memory effects on mobile and extractable soil water pools
Krug et al. Long-term origination rates are reset only at mass extinctions
TW200638422A (en) Magnetic random access memory device
US9899079B2 (en) Memory devices
US10134469B1 (en) Read operation with data latch and signal termination for 1TNR memory array
US10489700B1 (en) Neuromorphic logic for an array of high on/off ratio non-volatile memory cells
CN104463563A (zh) 一种信息处理方法及电子设备
Frank North Korea's Foreign Trade
Pedersen Abstainers: a risk group?
Popovic et al. Trace and major elements in ash of “Nikola Tesla A” power plant dump (I)—Leached concentrations and environmental implications
Rathod et al. Comparative analysis of SEU in FINFET SRAM cells for superthreshold and subthreshold supply voltage operation
Farmaner Myanmar 2020–Rohingya citizenship: now or never?
Bowler-Hill 20180813_Need Help with Your Library Questions Make an Appointment with a Reference Librarian Today
Bérubé-Sasseville Pierre Anctil," À chacun ses juifs: 60 éditoriaux pour comprendre la position du Devoir à l’égard des Juifs. 1910-1947"
Witz et al. Response to comment on textquoteleftInitiation of chromosome replication controls both division and replication cycles in E. coli through a double-adder mechanismtextquoteright
Perriguey et al. RELATIONSHIP BETWEEN INITIAL ENVIRONMENTAL CONDITIONS AND BIOTIC EXTINCTION EVENTS FROM THE LAST~ 540 MILLION YEARS
Boiveiri et al. Hegel, Marx and the contemporary world
Kim Usefulness and Development Plan of Jeju World Islands Culture Festival To Be a Global Festival
Hall Book review: The presidency of Barack Obama: a first historical assessment edited by Julian Zelizer
Loskutov et al. Forced Non-autonomous Empirical Model of the Mid-Pleistocene Transition

Legal Events

Date Code Title Description
PLFP Fee payment

Year of fee payment: 6

PLFP Fee payment

Year of fee payment: 7

PLFP Fee payment

Year of fee payment: 8

PLFP Fee payment

Year of fee payment: 10

PLFP Fee payment

Year of fee payment: 11

TP Transmission of property

Owner name: UNIVERSITE PARIS-SACLAY, FR

Effective date: 20210916

PLFP Fee payment

Year of fee payment: 12

PLFP Fee payment

Year of fee payment: 13

PLFP Fee payment

Year of fee payment: 14