FR2968456A1 - High frequency radiation shielded integrated circuit for mobile phone, has conductive vias evenly arranged to connect metal layer with conductive pads, where metal layer is covered with protective layer made of radiation absorbing material - Google Patents

High frequency radiation shielded integrated circuit for mobile phone, has conductive vias evenly arranged to connect metal layer with conductive pads, where metal layer is covered with protective layer made of radiation absorbing material Download PDF

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Publication number
FR2968456A1
FR2968456A1 FR1060193A FR1060193A FR2968456A1 FR 2968456 A1 FR2968456 A1 FR 2968456A1 FR 1060193 A FR1060193 A FR 1060193A FR 1060193 A FR1060193 A FR 1060193A FR 2968456 A1 FR2968456 A1 FR 2968456A1
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Prior art keywords
integrated circuit
metal layer
chip
face
frame
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FR1060193A
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French (fr)
Inventor
Jean-Francois Carpentier
Romain Coffy
Eric Saugier
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STMicroelectronics SA
STMicroelectronics Grenoble 2 SAS
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STMicroelectronics SA
STMicroelectronics Grenoble 2 SAS
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Priority to FR1060193A priority Critical patent/FR2968456A1/en
Publication of FR2968456A1 publication Critical patent/FR2968456A1/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01072—Hafnium [Hf]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The integrated circuit has an integrated circuit chip (11) including a lower surface comprising a metallization array (12). An insulating frame (14) having thickness similar to that of the chip is integrated to the chip. A metal layer (16) covers the chip and frame assembly from a side of an upper surface of the chip. Conductive vias (17) are evenly arranged for connecting the metal layer to conductive pads (22) formed on periphery of the frame, from a side of the lower chip surface. The metal layer is covered with a protective layer (35) made of high frequency radiation absorbing material. An independent claim is also included for a method for manufacturing an integrated circuit.

Description

B10685 - 10-GR1-174 1 CIRCUIT INTÉGRÉ PROTÉGÉ CONTRE LES RAYONNEMENTS HF B10685 - 10-GR1-174 1 INTEGRATED CIRCUIT PROTECTED AGAINST HF RADIATION

Domaine de l'invention La présente invention concerne la protection de circuits intégrés contre des rayonnements HF. Exposé de l'art antérieur Il existe de nombreuses ambiances dans lesquelles des circuits intégrés doivent être protégés contre des rayonnements HF éventuellement produits par des circuits voisins, par exemple dans des téléphones portables. Dans d'autres cas, il s'agit de protéger des circuits analogiques contre des impulsions haute fréquence produites par la commutation de circuits logiques voisins. Comme l'illustre la figure 1, quand plusieurs circuits 1, 2 sont montés, par exemple en montage en surface par des billes 3 sur une carte de circuit imprimé, le procédé le plus couramment utilisé pour réaliser une telle protection ou blindage consiste à entourer le circuit intégré à protéger, ici le circuit 1, d'un capot métallique 7. Bien entendu, ceci complique le montage et exige des opérations supplémentaires, sans compter le coût du capot métallique. Field of the Invention The present invention relates to the protection of integrated circuits against HF radiation. BACKGROUND OF THE PRIOR ART There are many environments in which integrated circuits must be protected against RF radiation possibly produced by neighboring circuits, for example in mobile telephones. In other cases, it is to protect analog circuits against high frequency pulses produced by the switching of neighboring logic circuits. As illustrated in Figure 1, when several circuits 1, 2 are mounted, for example in surface mounting by balls 3 on a printed circuit board, the most commonly used method to achieve such protection or shielding is to surround the integrated circuit to protect, here the circuit 1, a metal cover 7. Of course, this complicates the assembly and requires additional operations, not to mention the cost of the metal cover.

On a également tenté d'utiliser des couches métalliques déposées sur des circuits intégrés pour réaliser ce blindage, mais toutes ces tentatives ont conduit à des coûts de B10685 - 10-GR1-174 It has also been attempted to use metal layers deposited on integrated circuits to carry out this shielding, but all these attempts have led to costs of B10685 - 10-GR1-174

2 fabrication relativement élevés ou à des protections peu efficaces. Il existe donc un besoin pour former des circuits intégrés blindés. 2 relatively high manufacturing or poorly effective protections. There is therefore a need to form shielded integrated circuits.

Résumé La présente invention vise à satisfaire ce besoin et à pallier au moins certains inconvénients des circuits intégrés blindés classiques. Plus particulièrement, des modes de réalisation de la présente invention visent à réaliser un circuit intégré blindé, destiné à être monté sur une carte de circuit imprimé dont la fabrication soit particulièrement simple. Ainsi, un mode de réalisation de la présente invention prévoit un circuit intégré protégé contre les rayonnements HF comprenant une puce de circuit intégré dont une première face comprend un réseau de métallisation ; un cadre isolant solidaire de la puce et de même épaisseur que celle-ci ; une couche métallique revêtant l'ensemble de la puce et du cadre du côté de la deuxième face de la puce ; et des nias conducteurs régulièrement répartis connectant la couche métallique à des plots conducteurs formés à la périphérie du cadre, du côté de la première face. Selon un mode de réalisation de la présente invention, des billes de connexion sont fixées à chacun des plots. Selon un mode de réalisation de la présente invention, des seconds plots sont reliés à des contacts reliés à des emplacements choisis du réseau de métallisation de la puce de circuit intégré, une seconde bille de connexion étant fixée à chacun des seconds plots. Selon un mode de réalisation de la présente invention, la couche métallique est revêtue d'une couche de protection. Selon un mode de réalisation de la présente invention, le circuit intégré est revêtu d'une couche de marquage. Selon un mode de réalisation de la présente invention, la couche de protection est en un matériau absorbant les rayonnements HF. Summary The present invention aims to meet this need and to overcome at least some disadvantages of conventional shielded integrated circuits. More particularly, embodiments of the present invention are directed to providing a shielded integrated circuit for mounting on a printed circuit board which is particularly simple to manufacture. Thus, an embodiment of the present invention provides an integrated circuit protected against RF radiation comprising an integrated circuit chip having a first face comprising a metallization network; an insulating frame integral with the chip and of the same thickness as the latter; a metal layer covering the entire chip and the frame on the side of the second face of the chip; and regularly distributed conductive niases connecting the metal layer to conductive pads formed at the periphery of the frame, on the side of the first face. According to one embodiment of the present invention, connection balls are attached to each of the pads. According to one embodiment of the present invention, second pads are connected to contacts connected to selected locations of the metallization network of the integrated circuit chip, a second connection ball being fixed to each of the second pads. According to one embodiment of the present invention, the metal layer is coated with a protective layer. According to an embodiment of the present invention, the integrated circuit is coated with a marking layer. According to one embodiment of the present invention, the protective layer is made of a material that absorbs HF radiation.

B10685 - 10-GR1-174 B10685 - 10-GR1-174

3 Selon un mode de réalisation de la présente invention, le circuit intégré est adapté à recevoir du côté de sa deuxième face une autre puce de circuit intégré. Un mode de réalisation de la présente invention comprend les étapes consistant à former un cadre en résine entourant une puce de circuit intégré ; revêtir la première face de l'ensemble du cadre et de la puce d'une couche isolante ; revêtir la deuxième face de l'ensemble du cadre et de la puce d'une couche métallique ; former à partir de la première face des nias venant contacter la couche métallique ; former, du côté de la première face, des contacts avec des zones choisies du réseau de métallisation ; et fixer des billes à des plots reliés aux nias et aux contacts. Brève description des dessins Ces objets, caractéristiques et avantages, ainsi que d'autres seront exposés en détail dans la description suivante de modes de réalisation particuliers faite à titre non-limitatif en relation avec les figures jointes parmi lesquelles : la figure 1, décrite précédemment, représente des circuits intégrés montés sur une carte du circuit imprimé ; la figure 2 est une vue en coupe schématique d'un circuit intégré blindé selon un mode de réalisation de la présente invention ; et la figure 3 est une vue de dessous schématique du 25 circuit intégré de la figure 2. Description détaillée La figure 2 représente une puce de circuit intégré 11 munie du côté de sa face inférieure d'un réseau de métallisation en plusieurs niveaux 12. Cette puce est insérée dans un cadre de 30 matériau isolant 14, couramment de la résine. La résine 14 a la même épaisseur que la puce. Du côté de la face supérieure de la puce, à l'opposé du réseau de métallisation, une couche d'un matériau conducteur 16, couramment un métal, par exemple du cuivre, est déposée sur 35 la puce 11 et le cadre 14. Du côté de la face inférieure, est B10685 - 10-GR1-174 According to one embodiment of the present invention, the integrated circuit is adapted to receive on the side of its second face another integrated circuit chip. An embodiment of the present invention comprises the steps of forming a resin frame surrounding an integrated circuit chip; coating the entire face of the frame and the chip with an insulating layer; to coat the second face of the entire frame and the chip with a metal layer; forming from the first face nias coming to contact the metal layer; forming, on the side of the first face, contacts with selected areas of the metallization network; and fix balls to studs connected to niases and contacts. BRIEF DESCRIPTION OF THE DRAWINGS These and other objects, features, and advantages will be set forth in detail in the following description of particular embodiments in a non-limiting manner with reference to the accompanying drawings, in which: FIG. 1, previously described , represents integrated circuits mounted on a circuit board; Figure 2 is a schematic sectional view of a shielded integrated circuit according to an embodiment of the present invention; and FIG. 3 is a diagrammatic bottom view of the integrated circuit of FIG. 2. DETAILED DESCRIPTION FIG. 2 represents an integrated circuit chip 11 provided on its lower face side with a multi-level metallization network 12. chip is inserted into a frame of insulating material 14, commonly resin. Resin 14 has the same thickness as the chip. On the side of the upper face of the chip, opposite the metallization network, a layer of a conductive material 16, commonly a metal, for example copper, is deposited on the chip 11 and the frame 14. side of the underside, is B10685 - 10-GR1-174

4 déposée uniformément une couche isolante 19. Des nias conducteurs 17 traversent le cadre à sa périphérie. Ces nias pourront être disposés selon plusieurs rangées décalées. Du côté supérieur, ces nias conducteurs sont en contact avec la couche métallique 16. Du côté inférieur, les nias 17 traversent la couche isolante 19. Sur la couche isolante 19 sont formées des régions métalliques 21 elles-mêmes en contact avec des plots 22 adaptés à recevoir des billes de connexion 23. Les billes 23 auront par exemple un diamètre de 0,3 mm et seront à un pas de 0,5 mm. La protection pourra être complétée au niveau de la carte de circuit imprimé par une plaque métallique venant refermer la cage de protection. De plus, des contacts 25 traversent la couche isolante 19 en des emplacements où le réseau de métallisation 12 de la puce de circuit intégré doit être connecté. Ces contacts 25 sont reliés par des régions métalliques 31 formées en même temps que les régions 21 à des plots 32 formés en même temps que les plots 22. Des billes de connexion 33 sont fixées (soudées) en même temps que les billes 23 aux plots 32. 4 uniformly deposited an insulating layer 19. Conductive nias 17 pass through the frame at its periphery. These nias can be arranged in several staggered rows. On the upper side, these conductive niass are in contact with the metal layer 16. On the lower side, the nias 17 pass through the insulating layer 19. On the insulating layer 19 are formed metal regions 21 themselves in contact with pads 22 adapted to receive the connecting balls 23. The balls 23 have for example a diameter of 0.3 mm and will be at a pitch of 0.5 mm. The protection may be completed at the printed circuit board by a metal plate which closes the protective cage. In addition, contacts 25 pass through the insulating layer 19 at locations where the metallization network 12 of the integrated circuit chip is to be connected. These contacts 25 are connected by metal regions 31 formed at the same time as the regions 21 to studs 32 formed at the same time as the studs 22. Connection balls 33 are fixed (welded) together with the balls 23 to the studs 32.

De préférence, la couche métallique supérieure 16 est revêtue d'une couche de protection 35. La couche 35 peut notamment être en un matériau absorbant les rayonnements, permettant de compléter l'efficacité de blindage de la couche métallique 16 et pourra par exemple être en un polyimide. Une couche supplémentaire, non représentée, peut également être prévue pour permettre le marquage du circuit intégré. Ensuite, le composant est de façon classique monté sur une carte de circuit imprimé, les billes 33 venant contacter des zones de contact du circuit imprimé destinées à la connexion du circuit intégré et les billes 23 venant en contact avec un plan de masse formé dans le circuit imprimé et destiné à compléter le blindage du circuit intégré. Comme cela est représenté dans la vue de dessous de la figure 3, les plots 23 sont de préférence disposés très près les uns des autres de façon à constituer une cage de Faraday B10685 - 10-GR1-174 Preferably, the upper metal layer 16 is coated with a protective layer 35. The layer 35 may in particular be made of a radiation-absorbing material, making it possible to complete the shielding efficiency of the metal layer 16 and may for example be able to a polyimide. An additional layer, not shown, may also be provided to allow the marking of the integrated circuit. Then, the component is conventionally mounted on a printed circuit board, the balls 33 coming to contact areas of the printed circuit for connecting the integrated circuit and the balls 23 coming into contact with a ground plane formed in the printed circuit and intended to complete the shielding of the integrated circuit. As shown in the bottom view of FIG. 3, the pads 23 are preferably arranged very close to one another so as to form a Faraday cage. B10685 - 10-GR1-174

protégeant latéralement le circuit intégré contre des rayonnements HF parasites. La structure décrite ci-dessus est particulièrement simple à fabriquer. Le fait de prévoir un circuit intégré 5 entouré d'un cadre isolant en résine de même épaisseur que ce circuit intégré est connu en lui-même pour assurer la connexion du circuit intégré et permettre d'avoir un plus grand nombre de billes de contact que si ces billes étaient formées seulement du côté de la face inférieure du circuit intégré. En outre, on a représenté les billes de contact 33 disposées selon une seule couronne. Elles pourront être disposées selon une ou plusieurs lignes ou selon plusieurs couronnes, de façon régulière ou non, et éventuellement, des billes de connexion pourront être disposées sous la puce de circuit intégré elle-même. laterally protecting the integrated circuit against parasitic RF radiation. The structure described above is particularly simple to manufacture. The fact of providing an integrated circuit 5 surrounded by a resin insulating frame of the same thickness as this integrated circuit is known in itself to ensure the connection of the integrated circuit and allow to have a greater number of contact beads than if these balls were formed only on the side of the underside of the integrated circuit. In addition, there is shown the contact balls 33 arranged in a single ring. They may be arranged in one or more lines or in several rings, regularly or not, and possibly, connection beads may be disposed under the integrated circuit chip itself.

Divers procédés de fabrication d'un circuit intégré blindé tel que ci-dessus pourront être envisagés en utilisant des procédés couramment utilisés en microélectronique. On pourra par exemple réaliser les étapes consistant à former un cadre 14 en résine entourant une puce de circuit intégré 11, 12 ; revêtir la première face de l'ensemble du cadre et de la puce d'une couche isolante ; revêtir la deuxième face de l'ensemble du cadre et de la puce d'une couche métallique 16 ; former à partir de la première face des nias 17 venant contacter la couche métallique 16 ; former, du côté de la première face, des contacts 25 avec des zones choisies du réseau de métallisation 12 ; et fixer des billes 23, 33 à des plots 22, 32 reliés aux nias et aux contacts. On notera que la formation de nias traversant une couche de résine est particulièrement simple. De plus les étapes ci-dessus pourront être mises en oeuvre dans différents ordres. Des modes de réalisation particuliers de la présente invention ont été décrits. Diverses variantes et modifications apparaîtront à l'homme de l'art. En particulier, on pourra prévoir de faire remonter, au moyen de nias traversant les couches 16 et 35, des pistes vers des plots disposés sur la B10685 - 10-GR1-174 Various methods of manufacturing a shielded integrated circuit as above may be envisaged using methods commonly used in microelectronics. For example, the steps of forming a resin frame 14 surrounding an integrated circuit chip 11, 12; coating the entire face of the frame and the chip with an insulating layer; coating the second face of the entire frame and the chip with a metal layer 16; forming from the first face nias 17 contacting the metal layer 16; forming, on the side of the first face, contacts 25 with selected areas of the metallization network 12; and fix balls 23, 33 to studs 22, 32 connected to nias and contacts. Note that the formation of nias crossing a layer of resin is particularly simple. In addition the above steps may be implemented in different orders. Particular embodiments of the present invention have been described. Various variations and modifications will be apparent to those skilled in the art. In particular, it will be possible to trace back, by means of niases passing through the layers 16 and 35, tracks towards pins arranged on the B10685 - 10-GR1-174

6 surface supérieure du composant, ces plots étant adaptés à recevoir une deuxième puce. On notera que, dans certains cas, la couche isolante 19 n'est pas nécessaire, notamment si la face exposée du réseau 5 de métallisation est déjà recouverte d'une couche isolante. 6 upper surface of the component, these pads being adapted to receive a second chip. Note that in some cases, the insulating layer 19 is not necessary, especially if the exposed face of the metallization network 5 is already covered with an insulating layer.

Claims (8)

REVENDICATIONS1. Circuit intégré protégé contre les rayonnements HF comprenant : une puce de circuit intégré (11) dont une première face comprend un réseau de métallisation (12) ; un cadre isolant (14) solidaire de la puce et de même épaisseur que celle-ci ; une couche métallique (16) revêtant l'ensemble de la puce et du cadre du côté de la deuxième face de la puce ; des nias conducteurs (17) régulièrement répartis connectant la couche métallique (16) à des plots conducteurs (22) formés à la périphérie du cadre, du côté de la première face. REVENDICATIONS1. An RF shielded integrated circuit comprising: an integrated circuit chip (11) having a first face including a metallization array (12); an insulating frame (14) integral with the chip and of the same thickness as the latter; a metal layer (16) coating the entire chip and the frame on the side of the second face of the chip; conductive niases (17) regularly distributed connecting the metal layer (16) to conductive pads (22) formed at the periphery of the frame, on the side of the first face. 2. Circuit intégré selon la revendication 1, dans lequel des billes de connexion (23) sont fixées à chacun des plots. 2. Integrated circuit according to claim 1, wherein connecting balls (23) are fixed to each of the pads. 3. Circuit intégré selon la revendication 1 ou 2, comprenant en outre des seconds plots (32) reliés à des contacts (25) reliés à des emplacements choisis du réseau de métallisation de la puce de circuit intégré, une seconde bille de connexion (33) étant fixée à chacun des seconds plots. An integrated circuit according to claim 1 or 2, further comprising second pads (32) connected to contacts (25) connected to selected locations in the metallization array of the integrated circuit chip, a second connecting ball (33). ) being attached to each of the second pads. 4. Circuit intégré selon l'une quelconque des revendications 1 à 3, dans lequel la couche métallique (16) est revêtue d'une couche de protection (35). Integrated circuit according to any one of claims 1 to 3, wherein the metal layer (16) is coated with a protective layer (35). 5. Circuit intégré selon l'une quelconque des revendi-25 cations 1 à 4, revêtu d'une couche de marquage. 5. Integrated circuit according to any one of revendi-cations 1 to 4, coated with a marking layer. 6. Circuit intégré selon la revendication 4, dans lequel la couche de protection (35) est en un matériau absorbant les rayonnements HF. An integrated circuit according to claim 4, wherein the protective layer (35) is of an HF radiation absorbing material. 7. Circuit intégré selon l'une quelconque des revendi-30 cations 1 à 6, adapté à recevoir du côté de sa deuxième face une autre puce de circuit intégré. 7. Integrated circuit according to any one of revendi-cations 1 to 6, adapted to receive on the side of its second face another integrated circuit chip. 8. Procédé de fabrication d'un circuit intégré selon la revendication 1, comprenant les étapes suivantes :B10685 - 10-GR1-174 8 former un cadre (14) en résine entourant une puce de circuit intégré (11, 12) ; revêtir la première face de l'ensemble du cadre et de la puce d'une couche isolante ; revêtir la deuxième face de l'ensemble du cadre et de la puce d'une couche métallique (16) ; former à partir de la première face des nias (17) venant contacter la couche métallique ; former, du côté de la première face, des contacts (25) avec des zones choisies du réseau de métallisation (12) ; et fixer des billes (23, 33) à des plots (22, 32) reliés aux nias et aux contacts. The method of manufacturing an integrated circuit according to claim 1, comprising the steps of: forming a resin frame (14) surrounding an integrated circuit chip (11, 12); coating the entire face of the frame and the chip with an insulating layer; coating the second face of the entire frame and the chip with a metal layer (16); forming, from the first face, niases (17) coming to contact the metal layer; forming, on the side of the first face, contacts (25) with selected areas of the metallization network (12); and attaching balls (23, 33) to studs (22, 32) connected to the niases and contacts.
FR1060193A 2010-12-07 2010-12-07 High frequency radiation shielded integrated circuit for mobile phone, has conductive vias evenly arranged to connect metal layer with conductive pads, where metal layer is covered with protective layer made of radiation absorbing material Pending FR2968456A1 (en)

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FR1060193A FR2968456A1 (en) 2010-12-07 2010-12-07 High frequency radiation shielded integrated circuit for mobile phone, has conductive vias evenly arranged to connect metal layer with conductive pads, where metal layer is covered with protective layer made of radiation absorbing material

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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009035962A2 (en) * 2007-09-13 2009-03-19 Freescale Semiconductor Inc. Electromagnetic shield formation for integrated circuit die package

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009035962A2 (en) * 2007-09-13 2009-03-19 Freescale Semiconductor Inc. Electromagnetic shield formation for integrated circuit die package

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