FR2967522B1 - Memoire non-volatile securisee - Google Patents
Memoire non-volatile securiseeInfo
- Publication number
- FR2967522B1 FR2967522B1 FR1004417A FR1004417A FR2967522B1 FR 2967522 B1 FR2967522 B1 FR 2967522B1 FR 1004417 A FR1004417 A FR 1004417A FR 1004417 A FR1004417 A FR 1004417A FR 2967522 B1 FR2967522 B1 FR 2967522B1
- Authority
- FR
- France
- Prior art keywords
- volatile memory
- secure non
- secure
- volatile
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/24—Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/22—Safety or protection circuits preventing unauthorised or accidental access to memory cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/20—Address safety or protection circuits, i.e. arrangements for preventing unauthorized or accidental access
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Security & Cryptography (AREA)
- Computer Hardware Design (AREA)
- Static Random-Access Memory (AREA)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1004417A FR2967522B1 (fr) | 2010-11-12 | 2010-11-12 | Memoire non-volatile securisee |
US13/294,843 US8432726B2 (en) | 2010-11-12 | 2011-11-11 | Secure non-volatile memory |
US13/836,690 US9406372B2 (en) | 2010-11-12 | 2013-03-15 | Secure non-volatile memory |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1004417A FR2967522B1 (fr) | 2010-11-12 | 2010-11-12 | Memoire non-volatile securisee |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2967522A1 FR2967522A1 (fr) | 2012-05-18 |
FR2967522B1 true FR2967522B1 (fr) | 2012-12-21 |
Family
ID=44119482
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR1004417A Expired - Fee Related FR2967522B1 (fr) | 2010-11-12 | 2010-11-12 | Memoire non-volatile securisee |
Country Status (2)
Country | Link |
---|---|
US (2) | US8432726B2 (fr) |
FR (1) | FR2967522B1 (fr) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9478271B2 (en) * | 2013-03-14 | 2016-10-25 | Seagate Technology Llc | Nonvolatile memory data recovery after power failure |
US20150278681A1 (en) * | 2014-04-01 | 2015-10-01 | Boise State University | Memory controlled circuit system and apparatus |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6931075B2 (en) * | 2001-04-05 | 2005-08-16 | Microchip Technology Incorporated | Event detection with a digital processor |
US6912150B2 (en) * | 2003-05-13 | 2005-06-28 | Lionel Portman | Reference current generator, and method of programming, adjusting and/or operating same |
US20050063212A1 (en) * | 2003-09-18 | 2005-03-24 | Michael Jacob | Reference circuit implemented to reduce the degradation of reference capacitors providing reference voltages for 1T1C FeRAM devices |
US7009905B2 (en) * | 2003-12-23 | 2006-03-07 | International Business Machines Corporation | Method and apparatus to reduce bias temperature instability (BTI) effects |
EP1818942B1 (fr) | 2006-02-14 | 2011-07-06 | Stmicroelectronics Sa | Dispositif de mémoire non volatile |
US8218380B2 (en) * | 2009-10-30 | 2012-07-10 | Apple Inc. | Degradation equalization for a memory |
US9646177B2 (en) * | 2011-04-29 | 2017-05-09 | Altera Corporation | Systems and methods for preventing data remanence in memory systems |
-
2010
- 2010-11-12 FR FR1004417A patent/FR2967522B1/fr not_active Expired - Fee Related
-
2011
- 2011-11-11 US US13/294,843 patent/US8432726B2/en active Active
-
2013
- 2013-03-15 US US13/836,690 patent/US9406372B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
FR2967522A1 (fr) | 2012-05-18 |
US20130223138A1 (en) | 2013-08-29 |
US8432726B2 (en) | 2013-04-30 |
US20120120716A1 (en) | 2012-05-17 |
US9406372B2 (en) | 2016-08-02 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |
Effective date: 20150731 |