FR2925223B1 - Procede d'assemblage avec marques enterrees - Google Patents

Procede d'assemblage avec marques enterrees

Info

Publication number
FR2925223B1
FR2925223B1 FR0759944A FR0759944A FR2925223B1 FR 2925223 B1 FR2925223 B1 FR 2925223B1 FR 0759944 A FR0759944 A FR 0759944A FR 0759944 A FR0759944 A FR 0759944A FR 2925223 B1 FR2925223 B1 FR 2925223B1
Authority
FR
France
Prior art keywords
assembling
labels
entered
entered labels
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0759944A
Other languages
English (en)
Other versions
FR2925223A1 (fr
Inventor
Bernard Aspar
Chrystelle Lagahe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Priority to FR0759944A priority Critical patent/FR2925223B1/fr
Priority to PCT/EP2008/067652 priority patent/WO2009077538A2/fr
Publication of FR2925223A1 publication Critical patent/FR2925223A1/fr
Application granted granted Critical
Publication of FR2925223B1 publication Critical patent/FR2925223B1/fr
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/544Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C3/00Assembling of devices or systems from individually processed components
    • B81C3/002Aligning microparts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185Joining of semiconductor bodies for junction formation
    • H01L21/187Joining of semiconductor bodies for junction formation by direct bonding
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00Forming microstructural systems
    • B81C2203/05Aligning components to be assembled
    • B81C2203/051Active alignment, e.g. using internal or external actuators, magnets, sensors, marks or marks detectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544Marks applied to semiconductor devices or parts
    • H01L2223/54453Marks applied to semiconductor devices or parts for use prior to dicing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544Marks applied to semiconductor devices or parts
    • H01L2223/54493Peripheral marks on wafers, e.g. orientation flats, notches, lot number
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
FR0759944A 2007-12-18 2007-12-18 Procede d'assemblage avec marques enterrees Expired - Fee Related FR2925223B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR0759944A FR2925223B1 (fr) 2007-12-18 2007-12-18 Procede d'assemblage avec marques enterrees
PCT/EP2008/067652 WO2009077538A2 (fr) 2007-12-18 2008-12-16 Procédé d'assemblage avec repères enterrés

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0759944A FR2925223B1 (fr) 2007-12-18 2007-12-18 Procede d'assemblage avec marques enterrees

Publications (2)

Publication Number Publication Date
FR2925223A1 FR2925223A1 (fr) 2009-06-19
FR2925223B1 true FR2925223B1 (fr) 2010-02-19

Family

ID=39616549

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0759944A Expired - Fee Related FR2925223B1 (fr) 2007-12-18 2007-12-18 Procede d'assemblage avec marques enterrees

Country Status (2)

Country Link
FR (1) FR2925223B1 (fr)
WO (1) WO2009077538A2 (fr)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2953643B1 (fr) 2009-12-08 2012-07-27 Soitec Silicon On Insulator Cellule memoire flash sur seoi disposant d'une seconde grille de controle enterree sous la couche isolante
FR2957193B1 (fr) 2010-03-03 2012-04-20 Soitec Silicon On Insulator Cellule a chemin de donnees sur substrat seoi avec grille de controle arriere enterree sous la couche isolante
US8508289B2 (en) 2009-12-08 2013-08-13 Soitec Data-path cell on an SeOI substrate with a back control gate beneath the insulating layer
FR2953641B1 (fr) 2009-12-08 2012-02-10 S O I Tec Silicon On Insulator Tech Circuit de transistors homogenes sur seoi avec grille de controle arriere enterree sous la couche isolante
FR2955203B1 (fr) 2010-01-14 2012-03-23 Soitec Silicon On Insulator Cellule memoire dont le canal traverse une couche dielectrique enterree
FR2955195B1 (fr) 2010-01-14 2012-03-09 Soitec Silicon On Insulator Dispositif de comparaison de donnees dans une memoire adressable par contenu sur seoi
FR2955200B1 (fr) 2010-01-14 2012-07-20 Soitec Silicon On Insulator Dispositif, et son procede de fabrication, disposant d'un contact entre regions semi-conductrices a travers une couche isolante enterree
FR2955204B1 (fr) 2010-01-14 2012-07-20 Soitec Silicon On Insulator Cellule memoire dram disposant d'un injecteur bipolaire vertical
FR2957186B1 (fr) 2010-03-08 2012-09-28 Soitec Silicon On Insulator Cellule memoire de type sram
FR2957449B1 (fr) 2010-03-11 2022-07-15 S O I Tec Silicon On Insulator Tech Micro-amplificateur de lecture pour memoire
FR2958441B1 (fr) 2010-04-02 2012-07-13 Soitec Silicon On Insulator Circuit pseudo-inverseur sur seoi
EP2375442A1 (fr) * 2010-04-06 2011-10-12 S.O.I.Tec Silicon on Insulator Technologies Procédé de fabrication d'un substrat semi-conducteur
EP2381470B1 (fr) 2010-04-22 2012-08-22 Soitec Dispositif semi-conducteur comprenant un transistor à effet de champ dans une structure silicium sur isolant
KR20150036268A (ko) 2012-06-29 2015-04-07 코닝 인코포레이티드 반도체 공정용 유리-세라믹 기판
FR3028257A1 (fr) * 2014-11-10 2016-05-13 Tronic's Microsystems Procede de fabrication d'un dispositif electromecanique et dispositif correspondant

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5869386A (en) * 1995-09-28 1999-02-09 Nec Corporation Method of fabricating a composite silicon-on-insulator substrate
US6372600B1 (en) * 1999-08-30 2002-04-16 Agere Systems Guardian Corp. Etch stops and alignment marks for bonded wafers
FR2848725B1 (fr) * 2002-12-17 2005-02-11 Commissariat Energie Atomique Procede de formation de motifs alignes de part et d'autre d'un film mince

Also Published As

Publication number Publication date
WO2009077538A2 (fr) 2009-06-25
WO2009077538A3 (fr) 2009-08-27
FR2925223A1 (fr) 2009-06-19

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Legal Events

Date Code Title Description
ST Notification of lapse

Effective date: 20120831