FR2895420B1 - Procede de fabrication d'une structure demontable en forme de plaque, en particulier en silicium, et application de ce procede. - Google Patents

Procede de fabrication d'une structure demontable en forme de plaque, en particulier en silicium, et application de ce procede.

Info

Publication number
FR2895420B1
FR2895420B1 FR0513367A FR0513367A FR2895420B1 FR 2895420 B1 FR2895420 B1 FR 2895420B1 FR 0513367 A FR0513367 A FR 0513367A FR 0513367 A FR0513367 A FR 0513367A FR 2895420 B1 FR2895420 B1 FR 2895420B1
Authority
FR
France
Prior art keywords
manufacturing
application
plate
especially silicon
dismantling structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0513367A
Other languages
English (en)
Other versions
FR2895420A1 (fr
Inventor
Bernard Aspar
Blanchard Christelle Lagahe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Tracit Technologies SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tracit Technologies SA filed Critical Tracit Technologies SA
Priority to FR0513367A priority Critical patent/FR2895420B1/fr
Priority to PCT/FR2006/002886 priority patent/WO2007074242A1/fr
Priority to DE112006003461T priority patent/DE112006003461T5/de
Priority to KR1020087015644A priority patent/KR20080107352A/ko
Priority to US12/087,093 priority patent/US20090301995A1/en
Priority to CNA2006800495633A priority patent/CN101351879A/zh
Publication of FR2895420A1 publication Critical patent/FR2895420A1/fr
Application granted granted Critical
Publication of FR2895420B1 publication Critical patent/FR2895420B1/fr
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02—Elements
    • C30B29/06—Silicon
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
    • C30B33/02—Heat treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
    • Y10T156/11—Methods of delaminating, per se; i.e., separating at bonding face
    • Y10T156/1153—Temperature change for delamination [e.g., heating during delaminating, etc.]

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Metallurgy (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Organic Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Materials Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Thermal Sciences (AREA)
  • Element Separation (AREA)
  • Recrystallisation Techniques (AREA)
  • Micromachines (AREA)
FR0513367A 2005-12-27 2005-12-27 Procede de fabrication d'une structure demontable en forme de plaque, en particulier en silicium, et application de ce procede. Expired - Fee Related FR2895420B1 (fr)

Priority Applications (6)

Application Number Priority Date Filing Date Title
FR0513367A FR2895420B1 (fr) 2005-12-27 2005-12-27 Procede de fabrication d'une structure demontable en forme de plaque, en particulier en silicium, et application de ce procede.
PCT/FR2006/002886 WO2007074242A1 (fr) 2005-12-27 2006-12-27 Procede de fabrication d’une structure demontable en forme de plaque, en particulier en silicium, et application de ce procede
DE112006003461T DE112006003461T5 (de) 2005-12-27 2006-12-27 Verfahren zur Herstellung einer zerlegbaren scheibenförmigen Struktur, insbesondere auf Silizium basierend, und Anwendung des Verfahrens
KR1020087015644A KR20080107352A (ko) 2005-12-27 2006-12-27 웨이퍼 형태의 탈착가능한 구조물 제작 방법
US12/087,093 US20090301995A1 (en) 2005-12-27 2006-12-27 Method for Making a Plate-Like Detachable Structure, in Particular Made of Silicon, and Use of Said Method
CNA2006800495633A CN101351879A (zh) 2005-12-27 2006-12-27 制造具体是由硅制成的板状可拆卸结构的方法以及该方法的应用

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0513367A FR2895420B1 (fr) 2005-12-27 2005-12-27 Procede de fabrication d'une structure demontable en forme de plaque, en particulier en silicium, et application de ce procede.

Publications (2)

Publication Number Publication Date
FR2895420A1 FR2895420A1 (fr) 2007-06-29
FR2895420B1 true FR2895420B1 (fr) 2008-02-22

Family

ID=36589085

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0513367A Expired - Fee Related FR2895420B1 (fr) 2005-12-27 2005-12-27 Procede de fabrication d'une structure demontable en forme de plaque, en particulier en silicium, et application de ce procede.

Country Status (6)

Country Link
US (1) US20090301995A1 (fr)
KR (1) KR20080107352A (fr)
CN (1) CN101351879A (fr)
DE (1) DE112006003461T5 (fr)
FR (1) FR2895420B1 (fr)
WO (1) WO2007074242A1 (fr)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7018909B2 (en) 2003-02-28 2006-03-28 S.O.I.Tec Silicon On Insulator Technologies S.A. Forming structures that include a relaxed or pseudo-relaxed layer on a substrate
FR2931293B1 (fr) 2008-05-15 2010-09-03 Soitec Silicon On Insulator Procede de fabrication d'une heterostructure support d'epitaxie et heterostructure correspondante
EP2151861A1 (fr) 2008-08-06 2010-02-10 S.O.I. TEC Silicon Passivation de structures semiconductrices gravées
TWI457984B (zh) 2008-08-06 2014-10-21 Soitec Silicon On Insulator 應變層的鬆弛方法
EP2151852B1 (fr) 2008-08-06 2020-01-15 Soitec Relâchement et transfert de couches tendues
EP2151856A1 (fr) 2008-08-06 2010-02-10 S.O.I. TEC Silicon Relâchement de couches tendues
EP2159836B1 (fr) 2008-08-25 2017-05-31 Soitec Couches de durcissement pour le relâchement de couches contraintes
FR2963982B1 (fr) 2010-08-20 2012-09-28 Soitec Silicon On Insulator Procede de collage a basse temperature
US8863809B2 (en) * 2011-11-14 2014-10-21 The Boeing Company Methods and systems for recycling of laminated materials
US9481566B2 (en) 2012-07-31 2016-11-01 Soitec Methods of forming semiconductor structures including MEMS devices and integrated circuits on opposing sides of substrates, and related structures and devices

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19840421C2 (de) * 1998-06-22 2000-05-31 Fraunhofer Ges Forschung Verfahren zur Fertigung von dünnen Substratschichten und eine dafür geeignete Substratanordnung
FR2816445B1 (fr) * 2000-11-06 2003-07-25 Commissariat Energie Atomique Procede de fabrication d'une structure empilee comprenant une couche mince adherant a un substrat cible
US6737337B1 (en) * 2001-04-27 2004-05-18 Advanced Micro Devices, Inc. Method of preventing dopant depletion in surface semiconductor layer of semiconductor-on-insulator (SOI) device
FR2860249B1 (fr) * 2003-09-30 2005-12-09 Michel Bruel Procede de fabrication d'une structure en forme de plaque, en particulier en silicium, application de procede, et structure en forme de plaque, en particulier en silicium

Also Published As

Publication number Publication date
FR2895420A1 (fr) 2007-06-29
WO2007074242A1 (fr) 2007-07-05
DE112006003461T5 (de) 2008-11-06
US20090301995A1 (en) 2009-12-10
KR20080107352A (ko) 2008-12-10
CN101351879A (zh) 2009-01-21

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Legal Events

Date Code Title Description
TP Transmission of property
CD Change of name or company name

Owner name: SOITEC, FR

Effective date: 20120423

ST Notification of lapse

Effective date: 20130830