FR2843827B1 - MECHANICAL RECYCLING OF A PLATE COMPRISING A STAMP LAYER AFTER SELECTING A THIN LAYER - Google Patents
MECHANICAL RECYCLING OF A PLATE COMPRISING A STAMP LAYER AFTER SELECTING A THIN LAYERInfo
- Publication number
- FR2843827B1 FR2843827B1 FR0210588A FR0210588A FR2843827B1 FR 2843827 B1 FR2843827 B1 FR 2843827B1 FR 0210588 A FR0210588 A FR 0210588A FR 0210588 A FR0210588 A FR 0210588A FR 2843827 B1 FR2843827 B1 FR 2843827B1
- Authority
- FR
- France
- Prior art keywords
- layer
- selecting
- plate
- stamp
- mechanical recycling
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02032—Preparing bulk and homogeneous wafers by reclaiming or re-processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Recrystallisation Techniques (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Priority Applications (8)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0210588A FR2843827B1 (en) | 2002-08-26 | 2002-08-26 | MECHANICAL RECYCLING OF A PLATE COMPRISING A STAMP LAYER AFTER SELECTING A THIN LAYER |
TW92123246A TWI322481B (en) | 2002-08-26 | 2003-08-25 | Mechanical recycling of a wafer comprising a buffer layer, after having taken a layer therefrom |
JP2005501224A JP2005537685A (en) | 2002-08-26 | 2003-08-26 | Mechanical recycling of the wafer after removing the layer from the wafer containing the buffer layer |
KR1020057003368A KR100854856B1 (en) | 2002-08-26 | 2003-08-26 | Mechanical recycling of a wafer comprising a buffer layer, after having taken a layer therefrom |
EP03792598A EP1532676A2 (en) | 2002-08-26 | 2003-08-26 | Mechanical recycling of a wafer comprising a buffer layer, after having taken a layer therefrom |
CNB038200538A CN100557785C (en) | 2002-08-26 | 2003-08-26 | Recirculation with wafer of buffer structure |
PCT/IB2003/004029 WO2004019403A2 (en) | 2002-08-26 | 2003-08-26 | Mechanical recycling of a wafer comprising a buffer layer, after having taken a layer therefrom |
US10/726,039 US7033905B2 (en) | 2002-08-26 | 2003-12-01 | Recycling of a wafer comprising a buffer layer after having separated a thin layer therefrom by mechanical means |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0210588A FR2843827B1 (en) | 2002-08-26 | 2002-08-26 | MECHANICAL RECYCLING OF A PLATE COMPRISING A STAMP LAYER AFTER SELECTING A THIN LAYER |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2843827A1 FR2843827A1 (en) | 2004-02-27 |
FR2843827B1 true FR2843827B1 (en) | 2005-05-27 |
Family
ID=31198316
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR0210588A Expired - Lifetime FR2843827B1 (en) | 2002-08-26 | 2002-08-26 | MECHANICAL RECYCLING OF A PLATE COMPRISING A STAMP LAYER AFTER SELECTING A THIN LAYER |
Country Status (2)
Country | Link |
---|---|
FR (1) | FR2843827B1 (en) |
TW (1) | TWI322481B (en) |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6306729B1 (en) * | 1997-12-26 | 2001-10-23 | Canon Kabushiki Kaisha | Semiconductor article and method of manufacturing the same |
JP3500063B2 (en) * | 1998-04-23 | 2004-02-23 | 信越半導体株式会社 | Method for recycling peeled wafer and silicon wafer for reuse |
US6326279B1 (en) * | 1999-03-26 | 2001-12-04 | Canon Kabushiki Kaisha | Process for producing semiconductor article |
US6468923B1 (en) * | 1999-03-26 | 2002-10-22 | Canon Kabushiki Kaisha | Method of producing semiconductor member |
WO2001011930A2 (en) * | 1999-08-10 | 2001-02-15 | Silicon Genesis Corporation | A cleaving process to fabricate multilayered substrates using low implantation doses |
US6573126B2 (en) * | 2000-08-16 | 2003-06-03 | Massachusetts Institute Of Technology | Process for producing semiconductor article using graded epitaxial growth |
-
2002
- 2002-08-26 FR FR0210588A patent/FR2843827B1/en not_active Expired - Lifetime
-
2003
- 2003-08-25 TW TW92123246A patent/TWI322481B/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
TWI322481B (en) | 2010-03-21 |
FR2843827A1 (en) | 2004-02-27 |
TW200411821A (en) | 2004-07-01 |
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Legal Events
Date | Code | Title | Description |
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CD | Change of name or company name |
Owner name: SOITEC, FR Effective date: 20120423 |
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PLFP | Fee payment |
Year of fee payment: 15 |
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PLFP | Fee payment |
Year of fee payment: 16 |
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PLFP | Fee payment |
Year of fee payment: 17 |
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PLFP | Fee payment |
Year of fee payment: 18 |
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PLFP | Fee payment |
Year of fee payment: 19 |
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PLFP | Fee payment |
Year of fee payment: 20 |