FR2804555B1 - Dispositif d'arbitrage sans niveau de tension metastable a la sortie - Google Patents

Dispositif d'arbitrage sans niveau de tension metastable a la sortie

Info

Publication number
FR2804555B1
FR2804555B1 FR0012026A FR0012026A FR2804555B1 FR 2804555 B1 FR2804555 B1 FR 2804555B1 FR 0012026 A FR0012026 A FR 0012026A FR 0012026 A FR0012026 A FR 0012026A FR 2804555 B1 FR2804555 B1 FR 2804555B1
Authority
FR
France
Prior art keywords
output
voltage level
arbitration device
metastable voltage
metastable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0012026A
Other languages
English (en)
Other versions
FR2804555A1 (fr
Inventor
Gerard M Blair
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HP Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of FR2804555A1 publication Critical patent/FR2804555A1/fr
Application granted granted Critical
Publication of FR2804555B1 publication Critical patent/FR2804555B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/26—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being duration, interval, position, frequency, or sequence
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H03K3/0375—Bistable circuits provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Logic Circuits (AREA)
  • Manipulation Of Pulses (AREA)
FR0012026A 2000-01-31 2000-09-21 Dispositif d'arbitrage sans niveau de tension metastable a la sortie Expired - Fee Related FR2804555B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/494,598 US6617900B1 (en) 2000-01-31 2000-01-31 Arbitrator with no metastable voltage levels on output

Publications (2)

Publication Number Publication Date
FR2804555A1 FR2804555A1 (fr) 2001-08-03
FR2804555B1 true FR2804555B1 (fr) 2005-02-18

Family

ID=23965135

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0012026A Expired - Fee Related FR2804555B1 (fr) 2000-01-31 2000-09-21 Dispositif d'arbitrage sans niveau de tension metastable a la sortie

Country Status (2)

Country Link
US (1) US6617900B1 (fr)
FR (1) FR2804555B1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7274221B2 (en) * 2005-11-29 2007-09-25 Micron Technology, Inc. Comparator circuit
US10122526B2 (en) 2017-04-01 2018-11-06 Intel Corporation Phase detector in a delay locked loop
CN109547011B (zh) * 2017-09-22 2022-11-29 智原科技股份有限公司 仲裁电路

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01134557A (ja) * 1987-11-19 1989-05-26 Mitsubishi Electric Corp アービタ回路
US4841178A (en) * 1988-02-23 1989-06-20 Northern Telecom Limited Asynchronous processor arbitration circuit
JP2569790B2 (ja) * 1989-03-13 1997-01-08 三菱電機株式会社 アービタ回路
JP3144794B2 (ja) * 1990-11-09 2001-03-12 株式会社日立製作所 マルチプロセッサシステム
US5089726A (en) * 1990-11-29 1992-02-18 International Business Machines Corporation Fast cycle time clocked amplifier
JP2523998B2 (ja) * 1991-01-31 1996-08-14 株式会社東芝 コンパレ―タ
US5315184A (en) * 1992-05-04 1994-05-24 Zilog, Inc. Self arbitrating auto resettable flag circuit
EP0820146A3 (fr) * 1996-07-16 1999-07-28 Seiko Epson Corporation Elément différentiel à retard servant à éviter l'oscillation en mode commun et l'hysterésis d'entrée

Also Published As

Publication number Publication date
US6617900B1 (en) 2003-09-09
FR2804555A1 (fr) 2001-08-03

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Legal Events

Date Code Title Description
ST Notification of lapse

Effective date: 20090529