FR2787233B1 - Procede pour verifier l'integrite des circuits de decodage d'une memoire - Google Patents
Procede pour verifier l'integrite des circuits de decodage d'une memoireInfo
- Publication number
- FR2787233B1 FR2787233B1 FR9815786A FR9815786A FR2787233B1 FR 2787233 B1 FR2787233 B1 FR 2787233B1 FR 9815786 A FR9815786 A FR 9815786A FR 9815786 A FR9815786 A FR 9815786A FR 2787233 B1 FR2787233 B1 FR 2787233B1
- Authority
- FR
- France
- Prior art keywords
- words
- memory
- decoding circuits
- integrity
- verifying
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/10—Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns
Landscapes
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9815786A FR2787233B1 (fr) | 1998-12-11 | 1998-12-11 | Procede pour verifier l'integrite des circuits de decodage d'une memoire |
US09/452,446 US6212112B1 (en) | 1998-12-11 | 1999-12-02 | Method to verify the integrity of the decoding circuits of a memory |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9815786A FR2787233B1 (fr) | 1998-12-11 | 1998-12-11 | Procede pour verifier l'integrite des circuits de decodage d'une memoire |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2787233A1 FR2787233A1 (fr) | 2000-06-16 |
FR2787233B1 true FR2787233B1 (fr) | 2001-02-16 |
Family
ID=9533964
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR9815786A Expired - Fee Related FR2787233B1 (fr) | 1998-12-11 | 1998-12-11 | Procede pour verifier l'integrite des circuits de decodage d'une memoire |
Country Status (2)
Country | Link |
---|---|
US (1) | US6212112B1 (fr) |
FR (1) | FR2787233B1 (fr) |
Families Citing this family (41)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6961567B1 (en) * | 2000-12-07 | 2005-11-01 | Palm, Inc. | Generic activation and registration framework for wireless devices |
TW567500B (en) * | 2002-07-09 | 2003-12-21 | Spirox Corp | Diagonal test method of flash memory |
FR2851075B1 (fr) * | 2003-02-11 | 2005-04-22 | St Microelectronics Sa | Procede pour tester l'integrite d'un circuit de decodage et d'une memoire y associee |
US7646645B2 (en) * | 2007-04-13 | 2010-01-12 | Atmel Corporation | Method and apparatus for testing the functionality of a page decoder |
US10275243B2 (en) | 2016-07-02 | 2019-04-30 | Intel Corporation | Interruptible and restartable matrix multiplication instructions, processors, methods, and systems |
EP4137941A1 (fr) | 2017-03-20 | 2023-02-22 | Intel Corporation | Systèmes, procédés et appareils pour l'addition, la soustraction et la multiplication matricielle |
WO2019009870A1 (fr) | 2017-07-01 | 2019-01-10 | Intel Corporation | Sauvegarde de contexte à taille d'état de sauvegarde variable |
US11816483B2 (en) | 2017-12-29 | 2023-11-14 | Intel Corporation | Systems, methods, and apparatuses for matrix operations |
US11789729B2 (en) | 2017-12-29 | 2023-10-17 | Intel Corporation | Systems and methods for computing dot products of nibbles in two tile operands |
US11093247B2 (en) | 2017-12-29 | 2021-08-17 | Intel Corporation | Systems and methods to load a tile register pair |
US11809869B2 (en) | 2017-12-29 | 2023-11-07 | Intel Corporation | Systems and methods to store a tile register pair to memory |
US11023235B2 (en) | 2017-12-29 | 2021-06-01 | Intel Corporation | Systems and methods to zero a tile register pair |
US11669326B2 (en) | 2017-12-29 | 2023-06-06 | Intel Corporation | Systems, methods, and apparatuses for dot product operations |
US10664287B2 (en) | 2018-03-30 | 2020-05-26 | Intel Corporation | Systems and methods for implementing chained tile operations |
US11093579B2 (en) | 2018-09-05 | 2021-08-17 | Intel Corporation | FP16-S7E8 mixed precision for deep learning and other algorithms |
US11579883B2 (en) | 2018-09-14 | 2023-02-14 | Intel Corporation | Systems and methods for performing horizontal tile operations |
US10970076B2 (en) | 2018-09-14 | 2021-04-06 | Intel Corporation | Systems and methods for performing instructions specifying ternary tile logic operations |
US10719323B2 (en) | 2018-09-27 | 2020-07-21 | Intel Corporation | Systems and methods for performing matrix compress and decompress instructions |
US10990396B2 (en) | 2018-09-27 | 2021-04-27 | Intel Corporation | Systems for performing instructions to quickly convert and use tiles as 1D vectors |
US10866786B2 (en) | 2018-09-27 | 2020-12-15 | Intel Corporation | Systems and methods for performing instructions to transpose rectangular tiles |
US10896043B2 (en) | 2018-09-28 | 2021-01-19 | Intel Corporation | Systems for performing instructions for fast element unpacking into 2-dimensional registers |
US10929143B2 (en) | 2018-09-28 | 2021-02-23 | Intel Corporation | Method and apparatus for efficient matrix alignment in a systolic array |
US10963256B2 (en) | 2018-09-28 | 2021-03-30 | Intel Corporation | Systems and methods for performing instructions to transform matrices into row-interleaved format |
US10963246B2 (en) | 2018-11-09 | 2021-03-30 | Intel Corporation | Systems and methods for performing 16-bit floating-point matrix dot product instructions |
US10929503B2 (en) | 2018-12-21 | 2021-02-23 | Intel Corporation | Apparatus and method for a masked multiply instruction to support neural network pruning operations |
US11886875B2 (en) | 2018-12-26 | 2024-01-30 | Intel Corporation | Systems and methods for performing nibble-sized operations on matrix elements |
US11294671B2 (en) | 2018-12-26 | 2022-04-05 | Intel Corporation | Systems and methods for performing duplicate detection instructions on 2D data |
US20200210517A1 (en) | 2018-12-27 | 2020-07-02 | Intel Corporation | Systems and methods to accelerate multiplication of sparse matrices |
US10922077B2 (en) | 2018-12-29 | 2021-02-16 | Intel Corporation | Apparatuses, methods, and systems for stencil configuration and computation instructions |
US10942985B2 (en) | 2018-12-29 | 2021-03-09 | Intel Corporation | Apparatuses, methods, and systems for fast fourier transform configuration and computation instructions |
US11269630B2 (en) | 2019-03-29 | 2022-03-08 | Intel Corporation | Interleaved pipeline of floating-point adders |
US11016731B2 (en) | 2019-03-29 | 2021-05-25 | Intel Corporation | Using Fuzzy-Jbit location of floating-point multiply-accumulate results |
US10990397B2 (en) | 2019-03-30 | 2021-04-27 | Intel Corporation | Apparatuses, methods, and systems for transpose instructions of a matrix operations accelerator |
US11175891B2 (en) | 2019-03-30 | 2021-11-16 | Intel Corporation | Systems and methods to perform floating-point addition with selected rounding |
US11403097B2 (en) | 2019-06-26 | 2022-08-02 | Intel Corporation | Systems and methods to skip inconsequential matrix operations |
US11334647B2 (en) | 2019-06-29 | 2022-05-17 | Intel Corporation | Apparatuses, methods, and systems for enhanced matrix multiplier architecture |
US11714875B2 (en) | 2019-12-28 | 2023-08-01 | Intel Corporation | Apparatuses, methods, and systems for instructions of a matrix operations accelerator |
US11972230B2 (en) | 2020-06-27 | 2024-04-30 | Intel Corporation | Matrix transpose and multiply |
US11941395B2 (en) | 2020-09-26 | 2024-03-26 | Intel Corporation | Apparatuses, methods, and systems for instructions for 16-bit floating-point matrix dot product instructions |
US12001385B2 (en) | 2020-12-24 | 2024-06-04 | Intel Corporation | Apparatuses, methods, and systems for instructions for loading a tile of a matrix operations accelerator |
US12001887B2 (en) | 2020-12-24 | 2024-06-04 | Intel Corporation | Apparatuses, methods, and systems for instructions for aligning tiles of a matrix operations accelerator |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE4223532A1 (de) * | 1992-07-17 | 1994-01-20 | Philips Patentverwaltung | Schaltungsanordnung zum Prüfen der Adressierung wenigstens einer Matrix |
US5490115A (en) * | 1994-07-29 | 1996-02-06 | Cypress Semiconductor Corp. | Method and apparatus for writing to memory cells in a minimum number of cycles during a memory test operation |
US5996106A (en) * | 1997-02-04 | 1999-11-30 | Micron Technology, Inc. | Multi bank test mode for memory devices |
US5954831A (en) * | 1997-10-08 | 1999-09-21 | Ects Inc. | Method for testing a memory device |
-
1998
- 1998-12-11 FR FR9815786A patent/FR2787233B1/fr not_active Expired - Fee Related
-
1999
- 1999-12-02 US US09/452,446 patent/US6212112B1/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
FR2787233A1 (fr) | 2000-06-16 |
US6212112B1 (en) | 2001-04-03 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |
Effective date: 20070831 |