FR2775531B1 - Additionneur numerique rapide - Google Patents

Additionneur numerique rapide

Info

Publication number
FR2775531B1
FR2775531B1 FR9802645A FR9802645A FR2775531B1 FR 2775531 B1 FR2775531 B1 FR 2775531B1 FR 9802645 A FR9802645 A FR 9802645A FR 9802645 A FR9802645 A FR 9802645A FR 2775531 B1 FR2775531 B1 FR 2775531B1
Authority
FR
France
Prior art keywords
digital adder
fast digital
fast
adder
digital
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR9802645A
Other languages
English (en)
Other versions
FR2775531A1 (fr
Inventor
Stephane Rossignol
Pierrette Faucherand
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
SGS Thomson Microelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics SA filed Critical SGS Thomson Microelectronics SA
Priority to FR9802645A priority Critical patent/FR2775531B1/fr
Priority to US09/252,181 priority patent/US6560625B1/en
Publication of FR2775531A1 publication Critical patent/FR2775531A1/fr
Application granted granted Critical
Publication of FR2775531B1 publication Critical patent/FR2775531B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G06F7/508—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using carry look-ahead circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/3808—Details concerning the type of numbers or the way they are handled
    • G06F2207/3812—Devices capable of handling different types of numbers
    • G06F2207/382—Reconfigurable for different fixed word lengths

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
FR9802645A 1998-02-27 1998-02-27 Additionneur numerique rapide Expired - Fee Related FR2775531B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR9802645A FR2775531B1 (fr) 1998-02-27 1998-02-27 Additionneur numerique rapide
US09/252,181 US6560625B1 (en) 1998-02-27 1999-02-18 Fast digital adder

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9802645A FR2775531B1 (fr) 1998-02-27 1998-02-27 Additionneur numerique rapide

Publications (2)

Publication Number Publication Date
FR2775531A1 FR2775531A1 (fr) 1999-09-03
FR2775531B1 true FR2775531B1 (fr) 2001-10-12

Family

ID=9523652

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9802645A Expired - Fee Related FR2775531B1 (fr) 1998-02-27 1998-02-27 Additionneur numerique rapide

Country Status (2)

Country Link
US (1) US6560625B1 (fr)
FR (1) FR2775531B1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6769007B2 (en) * 2001-04-05 2004-07-27 Sun Microsystems, Inc. Adder circuit with a regular structure
US8464129B2 (en) * 2008-08-15 2013-06-11 Lsi Corporation ROM list-decoding of near codewords

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1249833B (it) * 1990-11-13 1995-03-28 Tong Lung Metal Ind Co Ltd Serratura a codice meccanico
FR2693287B1 (fr) * 1992-07-03 1994-09-09 Sgs Thomson Microelectronics Sa Procédé pour effectuer des calculs numériques, et unité arithmétique pour la mise en Óoeuvre de ce procédé.
US5396435A (en) * 1993-02-10 1995-03-07 Vlsi Technology, Inc. Automated circuit design system and method for reducing critical path delay times
TW269074B (en) * 1994-10-14 1996-01-21 Ibm Circuit which includes cells with high fanout requirements which has a reduced RC delay
US5633820A (en) * 1995-06-05 1997-05-27 International Business Machines Corporation Self-resetting CMOS parallel adder with a bubble pipelined architecture, tri-rail merging logic, and enhanced testability
US6134576A (en) * 1998-04-30 2000-10-17 Mentor Graphics Corporation Parallel adder with independent odd and even sum bit generation cells

Also Published As

Publication number Publication date
FR2775531A1 (fr) 1999-09-03
US6560625B1 (en) 2003-05-06

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Legal Events

Date Code Title Description
CD Change of name or company name
ST Notification of lapse

Effective date: 20071030