FR2755552B1 - Dispositif de recopie d'un signal d'horloge d'entree a frequence non continue - Google Patents
Dispositif de recopie d'un signal d'horloge d'entree a frequence non continueInfo
- Publication number
- FR2755552B1 FR2755552B1 FR9613523A FR9613523A FR2755552B1 FR 2755552 B1 FR2755552 B1 FR 2755552B1 FR 9613523 A FR9613523 A FR 9613523A FR 9613523 A FR9613523 A FR 9613523A FR 2755552 B1 FR2755552 B1 FR 2755552B1
- Authority
- FR
- France
- Prior art keywords
- recognizing
- clock signal
- input clock
- frequency input
- continuous frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/181—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a numerical count result being used for locking the loop, the counter counting during fixed time intervals
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
- H03L7/0994—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising an accumulator
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
- H04J3/0632—Synchronisation of packets and cells, e.g. transmission of voice via a packet network, circuit emulation service [CES]
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Computer Hardware Design (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9613523A FR2755552B1 (fr) | 1996-11-06 | 1996-11-06 | Dispositif de recopie d'un signal d'horloge d'entree a frequence non continue |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9613523A FR2755552B1 (fr) | 1996-11-06 | 1996-11-06 | Dispositif de recopie d'un signal d'horloge d'entree a frequence non continue |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2755552A1 FR2755552A1 (fr) | 1998-05-07 |
FR2755552B1 true FR2755552B1 (fr) | 1999-01-08 |
Family
ID=9497370
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR9613523A Expired - Fee Related FR2755552B1 (fr) | 1996-11-06 | 1996-11-06 | Dispositif de recopie d'un signal d'horloge d'entree a frequence non continue |
Country Status (1)
Country | Link |
---|---|
FR (1) | FR2755552B1 (fr) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
IT1308746B1 (it) * | 1999-06-22 | 2002-01-10 | Cselt Centro Studi Lab Telecom | Dispositivo per la ricostruzione della temporizzazione di un canaledati trasportato su rete a pacchetto e relativo procedimento. |
US20020039211A1 (en) * | 1999-09-24 | 2002-04-04 | Tian Shen | Variable rate high-speed input and output in optical communication networks |
ATE388542T1 (de) * | 1999-12-13 | 2008-03-15 | Broadcom Corp | Sprach-durchgangsvorrichtung mit sprachsynchronisierung in abwärtsrichtung |
US7228077B2 (en) | 2000-05-12 | 2007-06-05 | Forster Energy Llc | Channel gain control for an optical communications system utilizing frequency division multiplexing |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2529733A1 (fr) * | 1982-06-30 | 1984-01-06 | Labo Cent Telecommunicat | Dispositif d'asservissement, en frequence, d'une horloge sur un signal exterieur de frequence moyenne tres precise mais comportant une gigue importante |
US4855683A (en) * | 1987-11-18 | 1989-08-08 | Bell Communications Research, Inc. | Digital phase locked loop with bounded jitter |
JP2937529B2 (ja) * | 1991-03-27 | 1999-08-23 | 日本電気株式会社 | クロック再生回路 |
US5483201A (en) * | 1993-09-30 | 1996-01-09 | At&T Corp. | Synchronization circuit using a high speed digital slip counter |
-
1996
- 1996-11-06 FR FR9613523A patent/FR2755552B1/fr not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
FR2755552A1 (fr) | 1998-05-07 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |
Effective date: 20140731 |