FR2754619A1 - Integrated circuit with active face covered with insulating layer - Google Patents

Integrated circuit with active face covered with insulating layer Download PDF

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Publication number
FR2754619A1
FR2754619A1 FR9612508A FR9612508A FR2754619A1 FR 2754619 A1 FR2754619 A1 FR 2754619A1 FR 9612508 A FR9612508 A FR 9612508A FR 9612508 A FR9612508 A FR 9612508A FR 2754619 A1 FR2754619 A1 FR 2754619A1
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FR
France
Prior art keywords
integrated circuit
insulating layer
outer edge
card
connection pads
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR9612508A
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French (fr)
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FR2754619B1 (en
Inventor
Pascal Billebaud
Michel Gouiller
Jean Pierre Kempf
Benoit Thevenot
Franck Roblot
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Solaic SA
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Solaic SA
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Priority to FR9612508A priority Critical patent/FR2754619B1/en
Publication of FR2754619A1 publication Critical patent/FR2754619A1/en
Application granted granted Critical
Publication of FR2754619B1 publication Critical patent/FR2754619B1/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07743—External electrical contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Credit Cards Or The Like (AREA)

Abstract

The integrated circuit has a semiconductor substrate (3) having an active face with external connection areas (4). It is partially covered with a insulating layer (5). The insulating layer has a non-rectilinear edge (6) between two adjacent connection areas. The edge is in the form of a broken line or has crenellated shape. The body of the card (1) has the integrated circuit fixed so it is proud of the surface of the card. The connection areas are connected lines to circuit paths made of a conductive polymer. The non-rectilinear edge slows progress of the liquid polymer, giving it time to harden.

Description

La présente invention concerne un circuit intégré ayant une face active recouverte d'une couche isolante et une carte à circuit intégré comportant un tel circuit intégré. The present invention relates to an integrated circuit having an active face covered with an insulating layer and to an integrated circuit card comprising such an integrated circuit.

On sait que lorsqu'un circuit intégré est implanté dans un corps de carte de façon à avoir une face active affleurant le corps de carte, cette face active comportant des plots de connexion auxquels sont reliés des lignes en polymère conducteur s'étendant à la surface du corps de carte, il est nécessaire que la face active du circuit intégré soit partiellement recouverte d'une couche isolante, par exemple une couche isolante en forme de cadre déposée sur la surface active du circuit intégré préalablement à l'implantation de celui-ci dans le corps de carte. It is known that when an integrated circuit is implanted in a card body so as to have an active face flush with the card body, this active face comprising connection pads to which lines of conductive polymer extending to the surface are connected. of the card body, it is necessary that the active face of the integrated circuit is partially covered with an insulating layer, for example an insulating layer in the form of a frame deposited on the active surface of the integrated circuit prior to the implantation thereof. in the card body.

Le circuit intégré est enfoncé dans le corps de carte au moyen d'un poinçon chauffant qui assure tout à la fois le ramollissement de la matière constituant le corps de carte et un appui sur le circuit intégré pour enfoncer celui-ci dans la matière ramollie. Lors de l'enfoncement du circuit intégré la matière ramollie tend à fluer et pour éviter qu'elle ne vienne recouvrir les plots de connexion du circuit intégré, on règle la course du poinçon chauffant pour que la face supérieure de la couche isolante du circuit intégré ne soit pas en-dessous du niveau de la face supérieure du corps de carte. En pratique la surface supérieure de la couche isolante est très légèrement audessus de la surface du corps de carte (de l'ordre de deux micromètres) . Le même problème survient si le circuit intégré est fixé dans une cavité réalisée préalablement dans le corps de carte en raison de l'impossibilité de fixer industriellement le circuit intégré de façon que la face supérieure du circuit intégré soit exactement coplanaire à la surface supérieure du corps de carte.The integrated circuit is pressed into the card body by means of a heating punch which ensures both the softening of the material constituting the card body and a support on the integrated circuit to push it into the softened material. When the integrated circuit is pushed in, the softened material tends to creep and to prevent it from covering the connection pads of the integrated circuit, the stroke of the heating punch is adjusted so that the upper face of the insulating layer of the integrated circuit is not below the level of the upper face of the card body. In practice, the upper surface of the insulating layer is very slightly above the surface of the card body (of the order of two micrometers). The same problem occurs if the integrated circuit is fixed in a cavity made beforehand in the card body because of the impossibility of industrially fixing the integrated circuit so that the upper face of the integrated circuit is exactly coplanar with the upper surface of the body. Map.

Le bord externe de la couche isolante forme donc une petite marche par rapport à la face du corps de carte dans laquelle le circuit intégré est implanté. Lors du dépôt d'un polymère à l'état liquide pour former les lignes conductrices qui s'étendent généralement perpendiculairement au bord de la couche isolante du circuit intégré, le polymère à l'état liquide à tendance à s'écouler selon des lois proches de la capillarité le long de la marche formée par le bord de la couche isolante du circuit intégré de sorte qu'il existe un risque de court-circuit entre deux lignes conductrices adjacentes, ce qui met la carte hors service. The outer edge of the insulating layer therefore forms a small step with respect to the face of the card body in which the integrated circuit is installed. When depositing a polymer in the liquid state to form the conductive lines which generally extend perpendicular to the edge of the insulating layer of the integrated circuit, the polymer in the liquid state tends to flow according to similar laws capillarity along the step formed by the edge of the insulating layer of the integrated circuit so that there is a risk of short circuit between two adjacent conductive lines, which puts the card out of service.

Selon l'invention on propose un circuit intégré comportant un substrat semi-conducteur ayant une face active pourvue de plots de connexion et partiellement recouverte d'une couche isolante qui, au moins entre deux plots de connexion adjacents, comporte un bord externe non rectiligne. According to the invention an integrated circuit is proposed comprising a semiconductor substrate having an active face provided with connection pads and partially covered with an insulating layer which, at least between two adjacent connection pads, has an external non-rectilinear edge.

Ainsi, on allonge la distance que doit parcourir le polymère conducteur à l'état liquide pour réunir deux lignes conductrices adjacentes et compte tenu de la faible vitesse de propagation du polymère conducteur à l'état liquide, cet allongement de la distance parcourue permet d'obtenir une solidification suffisante du polymère conducteur pour arrêter sa progression avant qu'un courtcircuit n'ait été réalisé entre les deux lignes conductrices adjacentes. Thus, the distance which the conductive polymer has to travel in the liquid state is extended to join two adjacent conductive lines and, taking into account the low speed of propagation of the conductive polymer in the liquid state, this extension of the distance traveled makes it possible to obtain sufficient solidification of the conductive polymer to stop its progression before a short circuit has been made between the two adjacent conductive lines.

Selon une version avantageuse de l'invention, le bord externe de la couche isolante a une forme de ligne brisée. Ainsi on ralentit encore la propagation du polymère conducteur à l'état liquide en raison de l'obstacle particulier que constitue un point anguleux dans le contour de la couche isolante. According to an advantageous version of the invention, the outer edge of the insulating layer has the shape of a broken line. Thus, the propagation of the conductive polymer in the liquid state is further slowed down due to the particular obstacle which constitutes an angular point in the contour of the insulating layer.

Selon encore un autre aspect avantageux de l'invention, le bord externe de la couche isolante a une forme en créneau. Ainsi, sur une faible distance on augmente le nombre de points anguleux et on ralentit encore la progression du polymère conducteur à l'état liquide. According to yet another advantageous aspect of the invention, the outer edge of the insulating layer has a square shape. Thus, over a short distance, the number of angular points is increased and the progression of the conductive polymer in the liquid state is further slowed down.

Selon un autre aspect de l'invention, celle-ci concerne également une carte à circuit intégré comportant un corps de carte dans lequel le circuit intégré selon l'invention est fixé, la carte à circuit intégré comportant en outre des lignes en polymère conducteur s'étendant à la surface du corps de carte et reliées aux plots de connexion du circuit intégré. Dans le cas d'un bord externe de la couche isolante en forme de créneau, au moins un des créneaux a de préférence une largeur inférieure à une distance séparant les bords en regard de deux lignes conductrices adjacentes. According to another aspect of the invention, it also relates to an integrated circuit card comprising a card body in which the integrated circuit according to the invention is fixed, the integrated circuit card further comprising lines of conductive polymer s extending to the surface of the card body and connected to the connection pads of the integrated circuit. In the case of an external edge of the insulating layer in the form of a slot, at least one of the slots preferably has a width less than a distance separating the edges opposite two adjacent conductive lines.

D'autres caractéristiques et avantages de l'invention apparaîtront à la lecture de la description qui va suivre d'un mode de réalisation particulier non limitatif de l'invention, en référence aux figures ci-jointes parmi lesquelles
- la figure 1 est une vue en perspective, en coupe selon la ligne I-I de la figure 2, d'une carte à circuit intégré selon l'invention avant la réalisation des lignes en polymère conducteur,
- la figure 2 est une vue partielle de dessus très agrandie de la carte à circuit intégré selon l'invention.Other characteristics and advantages of the invention will appear on reading the following description of a particular non-limiting embodiment of the invention, with reference to the attached figures among which
FIG. 1 is a perspective view, in section along line II of FIG. 2, of an integrated circuit card according to the invention before the lines of conductive polymer are produced,
- Figure 2 is a partial enlarged top view of the integrated circuit card according to the invention.

En référence aux figures, la carte à circuit intégré selon l'invention comporte de façon connue en soi un corps de carte 1 dans lequel est fixé, par exemple par enfoncement à chaud, un circuit intégré 2 comportant un substrat semi-conducteur 3 ayant une face active pourvue de plots de connexion 4. De façon également connue en soi la face active du circuit intégré est recouverte d'une couche isolante 5, par exemple une couche isolante en forme de cadre comme illustré sur les figures. With reference to the figures, the integrated circuit card according to the invention comprises, in a manner known per se, a card body 1 in which is fixed, for example by hot pressing, an integrated circuit 2 comprising a semiconductor substrate 3 having a active face provided with connection pads 4. In a manner also known per se, the active face of the integrated circuit is covered with an insulating layer 5, for example an insulating layer in the form of a frame as illustrated in the figures.

Le circuit intégré est fixé dans le corps de carte de façon que sa face supérieure affleure le corps de carte. Ainsi qu'il a été indiqué ci-dessus, la face supérieure de la couche isolante est très légèrement décalée par rapport à la face supérieure du corps de carte de sorte que le bord externe 6 de la couche isolante forme une marche de très faible épaisseur par rapport à la surface du corps de carte. The integrated circuit is fixed in the card body so that its upper face is flush with the card body. As indicated above, the upper face of the insulating layer is very slightly offset from the upper face of the card body so that the outer edge 6 of the insulating layer forms a step of very small thickness relative to the surface of the card body.

Selon l'invention on prévoit de réaliser la couche isolante 5 de façon que son bord externe 6 ait une forme non rectiligne au moins entre deux plots de connexion adjacents. According to the invention, provision is made to produce the insulating layer 5 so that its external edge 6 has a non-rectilinear shape at least between two adjacent connection pads.

Comme illustré sur les figures, le bord externe 6 de la couche isolante comporte de préférence des créneaux 7 dont la largeur 1 est inférieure à la distance D séparant les bords en regard de deux lignes conductrices 8 adjacentes en polymère conducteur reliées aux plots de connexion 4. As illustrated in the figures, the outer edge 6 of the insulating layer preferably has slots 7 whose width 1 is less than the distance D separating the facing edges from two adjacent conductive lines 8 made of conductive polymer connected to the connection pads 4 .

Ainsi, on s'assure que lors de la réalisation des lignes conductrices 8 au moyen d'un polymère conducteur à l'état liquide après implantation du circuit intégré dans la carte, le polymère conducteur liquide qui a tendance à suivre le bord externe 6 selon des lois proches de la capillarité, rencontre nécessairement au moins un point anguleux avant d'atteindre la ligne conductrice adjacente de sorte que sa propagation est ralentie pendant un temps suffisant pour obtenir une solidification du polymère conducteur avant qu'il n'ait effectivement réalisé un court-circuit avec la ligne conductrice 8 adjacente. Thus, it is ensured that during the production of the conductive lines 8 by means of a conductive polymer in the liquid state after implantation of the integrated circuit in the card, the liquid conductive polymer which tends to follow the external edge 6 according to laws close to capillarity, necessarily meet at least one angular point before reaching the adjacent conductive line so that its propagation is slowed down for a time sufficient to solidify the conductive polymer before it has actually produced a short circuit with the adjacent conductive line 8.

On remarquera que la couche isolante 5 étant généralement déposée par photogravure, il suffit pour réaliser l'invention de prévoir un dessin approprié sur le masque d'insolation de sorte que l'invention peut être réalisée sans aucune augmentation de coût par rapport aux réalisations antérieures. It will be noted that the insulating layer 5 is generally deposited by photoengraving, it suffices to carry out the invention to provide an appropriate design on the insulating mask so that the invention can be carried out without any increase in cost compared to previous embodiments .

Bien entendu l'invention n'est pas limitée au mode de réalisation décrit et on peut y apporter des variantes de réalisation sans sortir du cadre de l'invention tel que défini par les revendications. Of course, the invention is not limited to the embodiment described and it is possible to make variant embodiments without departing from the scope of the invention as defined by the claims.

En particulier, bien que l'invention ait été illustrée avec un circuit intégré comportant un bord externe en forme de ligne brisée et plus particulièrement selon une forme en créneau, on peut également réaliser l'invention en prévoyant un bord externe curviligne pour la couche isolante. In particular, although the invention has been illustrated with an integrated circuit comprising an outer edge in the form of a broken line and more particularly in a square shape, it is also possible to carry out the invention by providing a curvilinear outer edge for the insulating layer .

Bien que l'invention ait été illustrée avec des créneaux 7 répartis sur tout le pourtour de la couche isolante, on peut prévoir des portions de bord non rectilignes seulement sur les parties du contour de la couche isolante sur lesquelles la distance entre deux plots de connexion est critique du point de vue du risque de courtcircuit entre les lignes conductrices adjacentes, c'est-àdire principalement lorsque deux lignes conductrices s'étendent l'une à côté de l'autre sur un même côté ou sur deux côtés adjacents du contour de la couche isolante. Although the invention has been illustrated with slots 7 distributed around the entire periphery of the insulating layer, non-rectilinear edge portions may be provided only on the parts of the contour of the insulating layer on which the distance between two connection pads is critical from the point of view of the risk of short circuit between the adjacent conductive lines, that is to say mainly when two conductive lines extend one beside the other on the same side or on two adjacent sides of the contour of the insulating layer.

Bien que les créneaux aient été représentés avec une forme rectangulaire, on peut prévoir des créneaux ayant une forme quelconque, par exemple triangulaire ou en queue d'aronde, voire même semi-circulaire. On peut également réaliser la couche isolante 5 sous forme d'un cadre de très faible largeur formant une ligne sinueuse autour des plots de connexion 4.  Although the slots have been shown with a rectangular shape, slots can be provided with any shape, for example triangular or dovetail, or even semi-circular. It is also possible to produce the insulating layer 5 in the form of a very narrow frame forming a sinuous line around the connection pads 4.

Claims (7)

REVENDICATIONS 1. Circuit intégré comportant un substrat semiconducteur (3) ayant une face active pourvue de plots de connexion (4) et partiellement recouverte d'une couche isolante (5), caractérisé en ce qu'au moins entre deux plots de connexion (4) adjacents, la couche isolante comporte un bord externe (6) non rectiligne. 1. Integrated circuit comprising a semiconductor substrate (3) having an active face provided with connection pads (4) and partially covered with an insulating layer (5), characterized in that at least between two connection pads (4) adjacent, the insulating layer has an outer edge (6) which is not straight. 2. Circuit intégré selon la revendication 1, caractérisé en ce que le bord externe (6) de la couche isolante a une forme de ligne brisée. 2. Integrated circuit according to claim 1, characterized in that the outer edge (6) of the insulating layer has the form of a broken line. 3. Circuit intégré selon la revendication 2, caractérisé en ce que le bord externe de la couche isolante a une forme en créneau (7). 3. Integrated circuit according to claim 2, characterized in that the outer edge of the insulating layer has a square shape (7). 4. Carte à circuit intégré comportant un corps de carte (1) dans lequel est fixé un circuit intégré (2) affleurant le corps de carte et comportant des plots de connexion (4) auxquels sont reliées des lignes en polymère conducteur (8) s'étendant à la surface du corps de carte, le circuit intégré étant partiellement recouvert d'une couche isolante (5), caractérisée en ce qu'au moins entre deux plots de connexion (4) adjacents, la couche isolante (5) comporte un bord externe (6) non rectiligne. 4. Integrated circuit card comprising a card body (1) in which an integrated circuit (2) is fixed flush with the card body and comprising connection pads (4) to which lines of conductive polymer (8) are connected extending to the surface of the card body, the integrated circuit being partially covered with an insulating layer (5), characterized in that at least between two adjacent connection pads (4), the insulating layer (5) comprises a outer edge (6) not straight. 5. Carte à circuit intégré selon la revendication 4, caractérisée en ce que le bord externe (6) de la couche isolante a une forme de ligne brisée. 5. Integrated circuit card according to claim 4, characterized in that the outer edge (6) of the insulating layer has the form of a broken line. 6. Carte à circuit intégré selon la revendication 5, caractérisée en ce que le bord externe (6) de la couche isolante a une forme en créneau (7). 6. Integrated circuit card according to claim 5, characterized in that the outer edge (6) of the insulating layer has a slot shape (7). 7. Carte à circuit intégré selon la revendication 6, caractérisée en ce qu'au moins un des créneaux (7) a une largeur (1) inférieure à une distance (D) séparant des bords en regard de deux lignes conductrices adjacentes.  7. Integrated circuit card according to claim 6, characterized in that at least one of the slots (7) has a width (1) less than a distance (D) separating opposite edges of two adjacent conductive lines.
FR9612508A 1996-10-14 1996-10-14 INTEGRATED CIRCUIT HAVING AN ACTIVE FACE COVERED WITH AN INSULATING LAYER AND INTEGRATED CIRCUIT CARD COMPRISING SAME Expired - Fee Related FR2754619B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR9612508A FR2754619B1 (en) 1996-10-14 1996-10-14 INTEGRATED CIRCUIT HAVING AN ACTIVE FACE COVERED WITH AN INSULATING LAYER AND INTEGRATED CIRCUIT CARD COMPRISING SAME

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Application Number Priority Date Filing Date Title
FR9612508A FR2754619B1 (en) 1996-10-14 1996-10-14 INTEGRATED CIRCUIT HAVING AN ACTIVE FACE COVERED WITH AN INSULATING LAYER AND INTEGRATED CIRCUIT CARD COMPRISING SAME

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FR2754619A1 true FR2754619A1 (en) 1998-04-17
FR2754619B1 FR2754619B1 (en) 1998-12-11

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002095816A1 (en) * 2001-05-21 2002-11-28 Infineon Technologies Ag Method for contacting an electrical component with a substrate comprising a conducting structure

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2671417A1 (en) * 1991-01-04 1992-07-10 Solaic Sa Process for manufacturing a memory card and memory card thus obtained
FR2701139A1 (en) * 1993-02-01 1994-08-05 Solaic Sa Process for installing a microcircuit on the body of an intelligent card and/or a memory card, and card including a microcircuit thus installed

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2671417A1 (en) * 1991-01-04 1992-07-10 Solaic Sa Process for manufacturing a memory card and memory card thus obtained
FR2701139A1 (en) * 1993-02-01 1994-08-05 Solaic Sa Process for installing a microcircuit on the body of an intelligent card and/or a memory card, and card including a microcircuit thus installed

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002095816A1 (en) * 2001-05-21 2002-11-28 Infineon Technologies Ag Method for contacting an electrical component with a substrate comprising a conducting structure
US6915945B2 (en) 2001-05-21 2005-07-12 Infineon Technologies Ag Method for contact-connecting an electrical component to a substrate having a conductor structure

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Publication number Publication date
FR2754619B1 (en) 1998-12-11

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