FR2752471B1 - Dispositif et procede pour traiter des interruptions de logiciel avec transfert d'argument - Google Patents

Dispositif et procede pour traiter des interruptions de logiciel avec transfert d'argument

Info

Publication number
FR2752471B1
FR2752471B1 FR9710438A FR9710438A FR2752471B1 FR 2752471 B1 FR2752471 B1 FR 2752471B1 FR 9710438 A FR9710438 A FR 9710438A FR 9710438 A FR9710438 A FR 9710438A FR 2752471 B1 FR2752471 B1 FR 2752471B1
Authority
FR
France
Prior art keywords
processing software
argument transfer
interruptions
software interruptions
argument
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR9710438A
Other languages
English (en)
Other versions
FR2752471A1 (fr
Inventor
Peter Song Seungyoon
A Mohamed Moataz
Trong Nguyen Le
Chul Park Heon
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of FR2752471A1 publication Critical patent/FR2752471A1/fr
Application granted granted Critical
Publication of FR2752471B1 publication Critical patent/FR2752471B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016—Decoding the operand specifier, e.g. specifier format
    • G06F9/30167—Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
    • G06F9/3879—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3887—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple data lanes [SIMD]

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Advance Control (AREA)
  • Complex Calculations (AREA)
  • Multi Processors (AREA)
FR9710438A 1996-08-19 1997-08-18 Dispositif et procede pour traiter des interruptions de logiciel avec transfert d'argument Expired - Fee Related FR2752471B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/699,295 US5996058A (en) 1996-08-19 1996-08-19 System and method for handling software interrupts with argument passing

Publications (2)

Publication Number Publication Date
FR2752471A1 FR2752471A1 (fr) 1998-02-20
FR2752471B1 true FR2752471B1 (fr) 1999-06-11

Family

ID=24808713

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9710438A Expired - Fee Related FR2752471B1 (fr) 1996-08-19 1997-08-18 Dispositif et procede pour traiter des interruptions de logiciel avec transfert d'argument

Country Status (7)

Country Link
US (1) US5996058A (fr)
JP (1) JPH10149297A (fr)
KR (1) KR100267090B1 (fr)
CN (1) CN1123837C (fr)
DE (1) DE19735869A1 (fr)
FR (1) FR2752471B1 (fr)
TW (1) TW353738B (fr)

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US6192073B1 (en) 1996-08-19 2001-02-20 Samsung Electronics Co., Ltd. Methods and apparatus for processing video data
JP3739888B2 (ja) * 1997-03-27 2006-01-25 株式会社ソニー・コンピュータエンタテインメント 情報処理装置および方法
US9092595B2 (en) 1997-10-08 2015-07-28 Pact Xpp Technologies Ag Multiprocessor having associated RAM units
US6697935B1 (en) * 1997-10-23 2004-02-24 International Business Machines Corporation Method and apparatus for selecting thread switch events in a multithreaded processor
US6202067B1 (en) * 1998-04-07 2001-03-13 Lucent Technologies, Inc. Method and apparatus for correct and complete transactions in a fault tolerant distributed database system
US6289446B1 (en) * 1998-09-29 2001-09-11 Axis Ab Exception handling utilizing call instruction with context information
US6347344B1 (en) * 1998-10-14 2002-02-12 Hitachi, Ltd. Integrated multimedia system with local processor, data transfer switch, processing modules, fixed functional unit, data streamer, interface unit and multiplexer, all integrated on multimedia processor
KR100308618B1 (ko) * 1999-02-27 2001-09-26 윤종용 단일 칩 상의 마이크로프로세서-코프로세서 시스템을 구비한 파이프라인 데이터 처리 시스템 및 호스트 마이크로프로세서와 코프로세서 사이의 인터페이스 방법
KR20010038857A (ko) * 1999-10-28 2001-05-15 박종섭 비동기 이동통신 시스템에서 메시지 인터페이스 방법
US6865663B2 (en) * 2000-02-24 2005-03-08 Pts Corporation Control processor dynamically loading shadow instruction register associated with memory entry of coprocessor in flexible coupling mode
US7133951B1 (en) * 2000-02-29 2006-11-07 Bourekas Philip A Alternate set of registers to service critical interrupts and operating system traps
KR100385233B1 (ko) * 2000-03-14 2003-05-23 삼성전자주식회사 데이터 프로세싱 시스템의 익스포넌트 유닛
US20020178313A1 (en) * 2001-03-30 2002-11-28 Gary Scott Paul Using software interrupts to manage communication between data processors
US7162573B2 (en) * 2003-06-25 2007-01-09 Intel Corporation Communication registers for processing elements
US7493435B2 (en) * 2003-10-06 2009-02-17 Intel Corporation Optimization of SMI handling and initialization
US7584344B2 (en) * 2006-05-02 2009-09-01 Freescale Semiconductor, Inc. Instruction for conditionally yielding to a ready thread based on priority criteria
US7831960B2 (en) * 2006-06-08 2010-11-09 Oracle America, Inc. Configuration tool with multi-level priority semantic
US7721034B2 (en) * 2006-09-29 2010-05-18 Dell Products L.P. System and method for managing system management interrupts in a multiprocessor computer system
US20080082710A1 (en) * 2006-09-29 2008-04-03 Dell Products L.P. System and method for managing system management interrupts in a multiprocessor computer system
CN101510190A (zh) * 2009-04-02 2009-08-19 北京中星微电子有限公司 一种基于自定义指令的多核通信***及方法
US9038073B2 (en) * 2009-08-13 2015-05-19 Qualcomm Incorporated Data mover moving data to accelerator for processing and returning result data based on instruction received from a processor utilizing software and hardware interrupts
US9378164B2 (en) * 2011-12-22 2016-06-28 Intel Corporation Interrupt return instruction with embedded interrupt service functionality
WO2013106210A1 (fr) * 2012-01-10 2013-07-18 Intel Corporation Appareil électronique à bancs de mémoire parallèles
CN104679585B (zh) * 2013-11-28 2017-10-24 中国航空工业集团公司第六三一研究所 浮点上下文切换方法
US10402527B2 (en) 2017-01-04 2019-09-03 Stmicroelectronics S.R.L. Reconfigurable interconnect
US11593609B2 (en) 2020-02-18 2023-02-28 Stmicroelectronics S.R.L. Vector quantization decoding hardware unit for real-time dynamic decompression for parameters of neural networks
US11507831B2 (en) 2020-02-24 2022-11-22 Stmicroelectronics International N.V. Pooling unit for deep learning acceleration
US11531873B2 (en) 2020-06-23 2022-12-20 Stmicroelectronics S.R.L. Convolution acceleration with embedded vector decompression
CN117311817B (zh) * 2023-11-30 2024-03-08 上海芯联芯智能科技有限公司 一种协处理器控制方法、装置、设备及存储介质

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US5182811A (en) * 1987-10-02 1993-01-26 Mitsubishi Denki Kabushiki Kaisha Exception, interrupt, and trap handling apparatus which fetches addressing and context data using a single instruction following an interrupt
US5109514A (en) * 1988-07-28 1992-04-28 Sun Microsystems, Inc. Method and apparatus for executing concurrent CO processor operations and precisely handling related exceptions
JP2858140B2 (ja) * 1988-10-19 1999-02-17 アポロ・コンピューター・インコーポレーテッド パイプラインプロセッサ装置および方法
US5278647A (en) * 1992-08-05 1994-01-11 At&T Bell Laboratories Video decoder using adaptive macroblock leak signals
US5319753A (en) * 1992-09-29 1994-06-07 Zilog, Inc. Queued interrupt mechanism with supplementary command/status/message information
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US5576765A (en) * 1994-03-17 1996-11-19 International Business Machines, Corporation Video decoder
US5510842A (en) * 1994-05-04 1996-04-23 Matsushita Electric Corporation Of America Parallel architecture for a high definition television video decoder having multiple independent frame memories
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US5594905A (en) * 1995-04-12 1997-01-14 Microsoft Corporation Exception handler and method for handling interrupts
US5668599A (en) * 1996-03-19 1997-09-16 International Business Machines Corporation Memory management for an MPEG2 compliant decoder

Also Published As

Publication number Publication date
FR2752471A1 (fr) 1998-02-20
US5996058A (en) 1999-11-30
CN1177147A (zh) 1998-03-25
JPH10149297A (ja) 1998-06-02
TW353738B (en) 1999-03-01
KR19980018068A (ko) 1998-06-05
DE19735869A1 (de) 1998-03-26
CN1123837C (zh) 2003-10-08
KR100267090B1 (ko) 2000-11-01

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Effective date: 20160429