FR2733067B1 - Dispositif et procede de commande de verrouillage - Google Patents

Dispositif et procede de commande de verrouillage

Info

Publication number
FR2733067B1
FR2733067B1 FR9604662A FR9604662A FR2733067B1 FR 2733067 B1 FR2733067 B1 FR 2733067B1 FR 9604662 A FR9604662 A FR 9604662A FR 9604662 A FR9604662 A FR 9604662A FR 2733067 B1 FR2733067 B1 FR 2733067B1
Authority
FR
France
Prior art keywords
control device
lock control
lock
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR9604662A
Other languages
English (en)
Other versions
FR2733067A1 (fr
Inventor
Kazuya Matsumoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of FR2733067A1 publication Critical patent/FR2733067A1/fr
Application granted granted Critical
Publication of FR2733067B1 publication Critical patent/FR2733067B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Memory System (AREA)
FR9604662A 1995-04-14 1996-04-15 Dispositif et procede de commande de verrouillage Expired - Fee Related FR2733067B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7088916A JP2776759B2 (ja) 1995-04-14 1995-04-14 ロックリクエスト制御装置

Publications (2)

Publication Number Publication Date
FR2733067A1 FR2733067A1 (fr) 1996-10-18
FR2733067B1 true FR2733067B1 (fr) 1997-10-10

Family

ID=13956257

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9604662A Expired - Fee Related FR2733067B1 (fr) 1995-04-14 1996-04-15 Dispositif et procede de commande de verrouillage

Country Status (3)

Country Link
US (1) US5893156A (fr)
JP (1) JP2776759B2 (fr)
FR (1) FR2733067B1 (fr)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5968157A (en) * 1997-01-23 1999-10-19 Sun Microsystems, Inc. Locking of computer resources
US6230230B1 (en) * 1998-12-03 2001-05-08 Sun Microsystems, Inc. Elimination of traps and atomics in thread synchronization
JP3391315B2 (ja) 1999-10-20 2003-03-31 日本電気株式会社 バス制御装置
US6986005B2 (en) * 2001-12-31 2006-01-10 Hewlett-Packard Development Company, L.P. Low latency lock for multiprocessor computer system
GB0409326D0 (en) * 2004-04-27 2004-06-02 Ibm Locker manager for managing access to shared resources
US7523260B2 (en) * 2005-12-22 2009-04-21 International Business Machines Corporation Propagating data using mirrored lock caches
WO2007099616A1 (fr) 2006-02-28 2007-09-07 Fujitsu Limited Système et procédé de commande exclusive d'adresse
US20160179707A1 (en) * 2014-12-19 2016-06-23 Lattice Semiconductor Corporation Sharing a Common Resource Via Multiple Interfaces

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5129089A (en) * 1987-12-18 1992-07-07 Digital Equipment Corporation Distributed interlock apparatus and distributed interlock management method
WO1989006011A1 (fr) * 1987-12-18 1989-06-29 Digital Equipment Corporation Gestion de l'enchevetrement d'adresses
US5317716A (en) * 1988-08-16 1994-05-31 International Business Machines Corporation Multiple caches using state information indicating if cache line was previously modified and type of access rights granted to assign access rights to cache line
US5175837A (en) * 1989-02-03 1992-12-29 Digital Equipment Corporation Synchronizing and processing of memory access operations in multiprocessor systems using a directory of lock bits
EP0384102A3 (fr) * 1989-02-22 1992-04-29 International Business Machines Corporation Mémoire cache de système multiprocesseur à structure de blocs de grande granularité et réservation exclusive desdits blocs
US5210848A (en) * 1989-02-22 1993-05-11 International Business Machines Corporation Multi-processor caches with large granularity exclusivity locking
US5214766A (en) * 1989-04-28 1993-05-25 International Business Machines Corporation Data prefetching based on store information in multi-processor caches
US5230070A (en) * 1989-09-08 1993-07-20 International Business Machines Corporation Access authorization table for multi-processor caches
US5289588A (en) * 1990-04-24 1994-02-22 Advanced Micro Devices, Inc. Interlock acquisition for critical code section execution in a shared memory common-bus individually cached multiprocessor system
US5297269A (en) * 1990-04-26 1994-03-22 Digital Equipment Company Cache coherency protocol for multi processor computer system
US5265232A (en) * 1991-04-03 1993-11-23 International Business Machines Corporation Coherence control by data invalidation in selected processor caches without broadcasting to processor caches not having the data
US5237694A (en) * 1991-05-30 1993-08-17 Advanced Micro Devices, Inc. Processing system and method including lock buffer for controlling exclusive critical problem accesses by each processor
EP0569605A1 (fr) * 1992-05-06 1993-11-18 International Business Machines Corporation Méthode pour contrôler l'accès de plusieurs processeurs à des données partagées
US5408629A (en) * 1992-08-13 1995-04-18 Unisys Corporation Apparatus and method for controlling exclusive access to portions of addressable memory in a multiprocessor system

Also Published As

Publication number Publication date
FR2733067A1 (fr) 1996-10-18
JPH08286968A (ja) 1996-11-01
JP2776759B2 (ja) 1998-07-16
US5893156A (en) 1999-04-06

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Legal Events

Date Code Title Description
ST Notification of lapse

Effective date: 20051230