FR2601792B1 - Systeme de traitement vectoriel - Google Patents

Systeme de traitement vectoriel

Info

Publication number
FR2601792B1
FR2601792B1 FR8710040A FR8710040A FR2601792B1 FR 2601792 B1 FR2601792 B1 FR 2601792B1 FR 8710040 A FR8710040 A FR 8710040A FR 8710040 A FR8710040 A FR 8710040A FR 2601792 B1 FR2601792 B1 FR 2601792B1
Authority
FR
France
Prior art keywords
treatment system
vector treatment
vector
treatment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR8710040A
Other languages
English (en)
Other versions
FR2601792A1 (fr
Inventor
Hideshi Ishii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of FR2601792A1 publication Critical patent/FR2601792A1/fr
Application granted granted Critical
Publication of FR2601792B1 publication Critical patent/FR2601792B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8053—Vector processors
    • G06F15/8076—Details on data register access
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/223—Execution means for microinstructions irrespective of the microinstruction function, e.g. decoding of microinstructions and nanoinstructions; timing of microinstructions; programmable logic arrays; delays and fan-out problems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G06F9/30014—Arithmetic instructions with variable precision
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Complex Calculations (AREA)
FR8710040A 1986-07-16 1987-07-16 Systeme de traitement vectoriel Expired - Fee Related FR2601792B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP16862686 1986-07-16
JP4132687 1987-02-26

Publications (2)

Publication Number Publication Date
FR2601792A1 FR2601792A1 (fr) 1988-01-22
FR2601792B1 true FR2601792B1 (fr) 1993-02-05

Family

ID=26380916

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8710040A Expired - Fee Related FR2601792B1 (fr) 1986-07-16 1987-07-16 Systeme de traitement vectoriel

Country Status (2)

Country Link
US (1) US4974198A (fr)
FR (1) FR2601792B1 (fr)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3304444B2 (ja) * 1992-11-30 2002-07-22 富士通株式会社 ベクトル処理装置
US6922771B2 (en) * 2002-04-24 2005-07-26 Portalplayer, Inc. Vector floating point unit
US9317251B2 (en) 2012-12-31 2016-04-19 Nvidia Corporation Efficient correction of normalizer shift amount errors in fused multiply add operations
US9778908B2 (en) 2014-07-02 2017-10-03 Via Alliance Semiconductor Co., Ltd. Temporally split fused multiply-accumulate operation
US9417839B1 (en) * 2014-11-07 2016-08-16 The United States Of America As Represented By The Secretary Of The Navy Floating point multiply-add-substract implementation
US11061672B2 (en) 2015-10-02 2021-07-13 Via Alliance Semiconductor Co., Ltd. Chained split execution of fused compound arithmetic operations
GB2553783B (en) 2016-09-13 2020-11-04 Advanced Risc Mach Ltd Vector multiply-add instruction
US10078512B2 (en) 2016-10-03 2018-09-18 Via Alliance Semiconductor Co., Ltd. Processing denormal numbers in FMA hardware
US11249767B2 (en) * 2019-02-05 2022-02-15 Dell Products L.P. Boot assist zero overhead flash extended file system

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3304417A (en) * 1966-05-23 1967-02-14 North American Aviation Inc Computer having floating point multiplication
US4287566A (en) * 1979-09-28 1981-09-01 Culler-Harrison Inc. Array processor with parallel operations per instruction
JPS57134774A (en) * 1981-02-13 1982-08-20 Hitachi Ltd Vector operating device
US4541046A (en) * 1981-03-25 1985-09-10 Hitachi, Ltd. Data processing system including scalar data processor and vector data processor
JPS58114274A (ja) * 1981-12-28 1983-07-07 Hitachi Ltd デ−タ処理装置
JPS592143A (ja) * 1982-06-29 1984-01-07 Hitachi Ltd 情報処理装置
US4507748A (en) * 1982-08-02 1985-03-26 International Telephone And Telegraph Corporation Associative processor with variable length fast multiply capability
US4594682A (en) * 1982-12-22 1986-06-10 Ibm Corporation Vector processing
US4589067A (en) * 1983-05-27 1986-05-13 Analogic Corporation Full floating point vector processor with dynamically configurable multifunction pipelined ALU
US4594679A (en) * 1983-07-21 1986-06-10 International Business Machines Corporation High speed hardware multiplier for fixed floating point operands
JPS6069746A (ja) * 1983-09-26 1985-04-20 Fujitsu Ltd ベクトル・デ−タ処理装置の制御方式
US4791555A (en) * 1983-10-24 1988-12-13 International Business Machines Corporation Vector processing unit
US4620275A (en) * 1984-06-20 1986-10-28 Wallach Steven J Computer system
US4736335A (en) * 1984-11-13 1988-04-05 Zoran Corporation Multiplier-accumulator circuit using latched sums and carries
US4682302A (en) * 1984-12-14 1987-07-21 Motorola, Inc. Logarithmic arithmetic logic unit
US4706191A (en) * 1985-07-31 1987-11-10 Sperry Corporation Local store for scientific vector processor
US4740893A (en) * 1985-08-07 1988-04-26 International Business Machines Corp. Method for reducing the time for switching between programs
US4862392A (en) * 1986-03-07 1989-08-29 Star Technologies, Inc. Geometry processor for graphics display system
US4777613A (en) * 1986-04-01 1988-10-11 Motorola Inc. Floating point numeric data processor

Also Published As

Publication number Publication date
FR2601792A1 (fr) 1988-01-22
US4974198A (en) 1990-11-27

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Legal Events

Date Code Title Description
ST Notification of lapse